Changeset 363 in xtideuniversalbios for trunk/XTIDE_Universal_BIOS/Inc
- Timestamp:
- Mar 26, 2012, 4:20:43 PM (13 years ago)
- google:author:
- aitotat@gmail.com
- Location:
- trunk/XTIDE_Universal_BIOS/Inc
- Files:
-
- 2 added
- 7 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/XTIDE_Universal_BIOS/Inc/ATA_ID.inc
r324 r363 3 3 %ifndef ATA_ID_INC 4 4 %define ATA_ID_INC 5 6 ; PIO Minimum Cycle Times (t0) 7 ; Timings for Advanced modes 3 and 4 can be read from ATA info WORDs 67 and 68 8 PIO_0_MIN_CYCLE_TIME_NS EQU 600 9 PIO_1_MIN_CYCLE_TIME_NS EQU 383 10 PIO_2_MIN_CYCLE_TIME_NS EQU 240 11 PIO_3_MIN_CYCLE_TIME_NS EQU 180 12 PIO_4_MIN_CYCLE_TIME_NS EQU 120 13 14 ; PIO Minimum Address Valid Times (t1) 15 PIO_0_MIN_ADDRESS_VALID_NS EQU 70 16 PIO_1_MIN_ADDRESS_VALID_NS EQU 50 17 PIO_2_MIN_ADDRESS_VALID_NS EQU 30 18 PIO_3_MIN_ADDRESS_VALID_NS EQU 30 19 PIO_4_MIN_ADDRESS_VALID_NS EQU 25 20 21 ; PIO Minimum Active Times (t2) 22 PIO_0_MIN_ACTIVE_TIME_NS EQU 165 23 PIO_1_MIN_ACTIVE_TIME_NS EQU 125 24 PIO_2_MIN_ACTIVE_TIME_NS EQU 100 25 PIO_3_MIN_ACTIVE_TIME_NS EQU 80 26 PIO_4_MIN_ACTIVE_TIME_NS EQU 70 27 28 ; PIO Minimum Recovery Times or Inactive Times (t2i) can be calculated 29 ; from Minimum Cycle Time (t0) - Minimum Active Time (t2) - Address Valid Time (t1). 30 ; I'm not sure about this calculation so correct me if I'm wrong! 31 ; Recovery time should be calculated at run time since Cycle Time t0 can be 32 ; read from ATA information (ATA2+) but most drives just report the 33 ; Min Cycle Times listed above. 34 35 5 36 6 37 ; ATA-1 Drive Information struct … … 32 63 resw 1 ; 50R 33 64 resb 1 ; 51[0-7]X 34 .bP IOTiming resb 1 ; 51[8-15]F, PIO data transfer cycle timing mode65 .bPioMode resb 1 ; 51[8-15]F, PIO data transfer cycle timing mode (0, 1 or 2) 35 66 resb 1 ; 52[0-7]X 36 67 .bDMATiming resb 1 ; 52[8-15]F, DMA data transfer cycle timing mode … … 163 194 A2_bBlockFlgs_VALID EQU (1<<0) ; Multiple sector setting (bBlockSel) is valid 164 195 196 ; ATA-2 Word 64, Advanced PIO transfer modes supported 197 A2_bPIOSupp_PIO3 EQU (1<<0) 198 A2_bPIOSupp_PIO4 EQU (1<<1) 199 165 200 166 201 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -
trunk/XTIDE_Universal_BIOS/Inc/BootMenu.inc
r294 r363 24 24 25 25 struc BOOTMENUINFO 26 .szDrvName resb MAX_HARD_DISK_NAME_LENGTH 27 resb 2 ; Zero word (ensures string terminates) 28 resb 4 ; padding to make BOOTMENUINFO size an even multiple of DPT size 26 .szDrvName resb MAX_HARD_DISK_NAME_LENGTH 27 resb 2 ; Zero word (ensures string terminates) 28 .wInitErrorFlags resb 2 ; Errors during initialization 29 30 %ifdef MODULE_ADVANCED_ATA 31 .wIdeBasePort resb 2 ; IDE Base Port 32 .wMinPioActiveTimeNs resb 2 ; Minimum PIO Active Time in ns 33 .wMinPioRecoveryTimeNs resb 2 ; Minimum PIO Recovery Time in ns 34 .wControllerID resb 2 ; Controller specific ID WORD 35 .wControllerBasePort resb 2 ; Advanced Controller port (not IDE port) 36 resb 12 ; padding to make BOOTMENUINFO size an even multiple of DPT size 37 38 %else 39 resb 2 ; padding to make BOOTMENUINFO size an even multiple of DPT size 40 %endif 29 41 endstruc 42 43 ; Flags for BOOTMENUINFO.wInitErrorFlags 44 FLG_INIT_FAILED_TO_SELECT_DRIVE EQU (1<<0) 45 FLG_INIT_FAILED_TO_INITIALIZE_CHS_PARAMETERS EQU (1<<1) 46 FLG_INIT_FAILED_TO_SET_WRITE_CACHE EQU (1<<2) 47 FLG_INIT_FAILED_TO_RECALIBRATE_DRIVE EQU (1<<3) 48 FLG_INIT_FAILED_TO_SET_BLOCK_MODE EQU (1<<4) 49 FLG_INIT_FAILED_TO_SET_PIO_MODE EQU (1<<5) 30 50 31 51 DPT_BOOTMENUINFO_SIZE_MULTIPLIER equ BOOTMENUINFO_size / LARGEST_DPT_SIZE -
trunk/XTIDE_Universal_BIOS/Inc/BootVars.inc
r294 r363 19 19 .rgbMnuStack: 20 20 .dwPostStack resb 4 ; POST stack pointer when entering INT 19h 21 .wMagicWord resb 2 ; I wish we didn't need this 21 22 .rgBootNfo: ; Array containing BOOTNFO structs 22 23 endstruc 24 25 ; Magic WORD to detect when BOOTVARS is available. 26 BOOTVARS_MAGIC_WORD EQU 1110011001100111b 27 23 28 24 29 -
trunk/XTIDE_Universal_BIOS/Inc/CustomDPT.inc
r358 r363 25 25 endstruc 26 26 27 ; DPT for ATA devices28 struc DPT_ATA ; 10 + 2 bytes = 12 bytes29 .dpt resb DPT_size30 31 ; Block size is specified in sectors (1, 2, 4, 8, 16, 32, 64 or 128)32 .wSetAndMaxBlock:33 .bSetBlock resb 1 ; Current block size (at least 1)34 .bMaxBlock resb 1 ; Maximum block size, 0 = block mode not supported35 endstruc36 37 %ifdef MODULE_SERIAL38 ; DPT for Serial devices39 struc DPT_SERIAL40 .dpt resb DPT_size41 42 .wSerialPortAndBaud:43 .bSerialPort resb 1 ; Serial connection I/O port address, divided by 444 .bSerialBaud resb 1 ; Serial connection baud rate divisor45 endstruc46 %endif47 48 LARGEST_DPT_SIZE EQU DPT_ATA_size49 50 51 27 ; Bit definitions for DPT.bFlagsLow 52 28 MASKL_DPT_CHS_SHIFT_COUNT EQU (7<<0) ; Bits 0...3, P-CHS to L-CHS bit shift count (0...4) … … 62 38 %endif 63 39 FLGH_DPT_INTERRUPT_IN_SERVICE EQU (1<<3) ; Set when waiting for IRQ 64 FLGH_DPT_RESET_nDRDY EQU (1<<4) ; Drive ready to accept commands65 FLGH_DPT_RESET_nINITPRMS EQU (1<<5) ; Initialize Device Parameters successful66 FLGH_DPT_RESET_nRECALIBRATE EQU (1<<6) ; Recalibrate successful67 FLGH_DPT_RESET_nSETBLOCK EQU (1<<7) ; Initialize Block Mode successful68 MASKH_DPT_RESET EQU 0F0h69 40 41 ; IDE device only 42 FLGH_DPT_INITERROR EQU (1<<7) 43 44 ; Serial device only 70 45 FLGH_DPT_SERIAL_FLOPPY EQU (1<<4) 71 46 FLGH_DPT_SERIAL_FLOPPY_TYPE_MASK EQU 0e0h … … 78 53 ADDRESSING_MODE_LBA28 EQU 2 ; 28-bit LBA Addressing Mode 79 54 ADDRESSING_MODE_LBA48 EQU 3 ; 48-bit LBA Addressing Mode 55 56 57 ; DPT for ATA devices 58 struc DPT_ATA ; 10 + 2 bytes = 12 bytes 59 .dpt resb DPT_size 60 61 ; Block size is specified in sectors (1, 2, 4, 8, 16, 32, 64 or 128) 62 .wSetAndMaxBlock: 63 .bSetBlock resb 1 ; Current block size (do not set to zero!) 64 .bMaxBlock resb 1 ; Maximum block size, 0 = block mode not supported 65 66 %ifdef MODULE_ADVANCED_ATA ; +2 extra bytes = 14 bytes 67 .bPioMode resb 1 68 .bDevice resb 1 69 %endif 70 endstruc 71 72 73 %ifdef MODULE_ADVANCED_ATA 74 ; Temporary extension for DPT_ATA. Contents will be copied to BOOTMENUINFO and 75 ; then these variables will be overridden by next DPT. 76 struc DPT_ADVANCED_ATA 77 .dpt_ata resb DPT_ATA_size 78 .wIdeBasePort resb 2 ; IDE Base Port 79 .wMinPioActiveTimeNs resb 2 ; Minimum PIO Active Time in ns 80 .wMinPioRecoveryTimeNs resb 2 ; Minimum PIO Recovery Time in ns 81 .wControllerID resb 2 ; Controller specific ID WORD 82 .wControllerBasePort resb 2 ; Advanced Controller port (not IDE port) 83 endstruc 84 %endif 85 86 87 %ifdef MODULE_SERIAL 88 ; DPT for Serial devices 89 struc DPT_SERIAL 90 .dpt resb DPT_size 91 92 .wSerialPortAndBaud: 93 .bSerialPort resb 1 ; Serial connection I/O port address, divided by 4 94 .bSerialBaud resb 1 ; Serial connection baud rate divisor 95 endstruc 96 %endif 97 98 99 ; This is the common size for all DPTs. All DPTs must be equal size. 100 LARGEST_DPT_SIZE EQU DPT_ATA_size 101 80 102 81 103 ; Number of Sectors per Track is fixed to 63 for LBA assist calculation. -
trunk/XTIDE_Universal_BIOS/Inc/IDE_8bit.inc
r152 r363 4 4 %ifndef IDE_8BIT_INC 5 5 %define IDE_8BIT_INC 6 7 ;-------------------------------------------------------------------- 8 ; UNROLL_SECTORS_IN_CX_TO_QWORDS 9 ; Parameters: 10 ; CX: Number of sectors in block 11 ; Returns: 12 ; CX: Number of QWORDs in block 13 ; Corrupts registers: 14 ; Nothing 15 ;-------------------------------------------------------------------- 16 %macro UNROLL_SECTORS_IN_CX_TO_QWORDS 0 17 %ifdef USE_186 18 shl cx, 6 19 %else 20 xchg cl, ch ; Sectors to WORDs (SHL CX, 8) 21 shr cx, 1 22 shr cx, 1 23 %endif 24 %endmacro 25 6 26 7 27 ;-------------------------------------------------------------------- -
trunk/XTIDE_Universal_BIOS/Inc/IdeRegisters.inc
r276 r363 84 84 FEATURE_ENABLE_WRITE_CACHE EQU 02h 85 85 FEATURE_DISABLE_WRITE_CACHE EQU 82h ; Can also be used to flush cache 86 FEATURE_SET_TRANSFER_MODE EQU 03h ; Transfe mode goes to the Sector Count Register 87 PIO_DEFAULT_MODE EQU 0h 88 PIO_DEFAULT_MODE_DISABLE_IORDY EQU 1h 89 PIO_FLOW_CONTROL_MODE_xxx EQU (1<<3) ; Bits 2...0 hold the PIO mode 86 90 87 91 -
trunk/XTIDE_Universal_BIOS/Inc/RomVars.inc
r361 r363 52 52 ; by holding down the ALT key at the end of drive detection. 53 53 ; (Conveniently, this is 8, a fact we exploit when testing the bit) 54 FLG_ROMVARS_MODULE_ADVATA EQU (1<<4) ; Here in case the configuration needs to know functionality is present 54 55 FLG_ROMVARS_MODULE_JRIDE EQU (1<<5) ; Here in case the configuration needs to know functionality is present 55 56 FLG_ROMVARS_MODULE_SERIAL EQU (1<<6) ; Here in case the configuration needs to know functionality is present … … 97 98 DEVICE_ATA_DEFAULT_PORT EQU 1F0h 98 99 DEVICE_ATA_DEFAULT_PORTCTRL EQU 3F0h 100 DEVICE_ATA_DEFAULT_SECONDARY_PORT EQU 170h 101 DEVICE_ATA_DEFAULT_SECONDARY_PORTCTRL EQU 370h 99 102 100 103 ; Device types for IDEVARS.bDevice
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