Changeset 363 in xtideuniversalbios for trunk/XTIDE_Universal_BIOS/Inc/ATA_ID.inc

Timestamp:

Mar 26, 2012, 4:20:43 PM (12 years ago)

Author:

aitotat@…

google:author:

aitotat@gmail.com

Message:

Changes to XTIDE Universal BIOS:

• Added Advanced ATA Module (MODULE_ADVANCED_ATA) with native support for QDI Vision QD6500 and QD6580 VLB IDE Controllers.
• Hopefully optimized IDE transfer functions for 8088 (replaced some memory accesses from WORD to BYTE).
• XT build does not fit in 8k at the moment!!!

File:

• trunk/XTIDE_Universal_BIOS/Inc/ATA_ID.inc (modified) (3 diffs)

trunk/XTIDE_Universal_BIOS/Inc/ATA_ID.inc

@@ -3 +3 @@
 %ifndef ATA_ID_INC
 %define ATA_ID_INC
+
+; PIO Minimum Cycle Times (t0)
+; Timings for Advanced modes 3 and 4 can be read from ATA info WORDs 67 and 68
+PIO_0_MIN_CYCLE_TIME_NS     EQU     600
+PIO_1_MIN_CYCLE_TIME_NS     EQU     383
+PIO_2_MIN_CYCLE_TIME_NS     EQU     240
+PIO_3_MIN_CYCLE_TIME_NS     EQU     180
+PIO_4_MIN_CYCLE_TIME_NS     EQU     120
+
+; PIO Minimum Address Valid Times (t1)
+PIO_0_MIN_ADDRESS_VALID_NS  EQU     70
+PIO_1_MIN_ADDRESS_VALID_NS  EQU     50
+PIO_2_MIN_ADDRESS_VALID_NS  EQU     30
+PIO_3_MIN_ADDRESS_VALID_NS  EQU     30
+PIO_4_MIN_ADDRESS_VALID_NS  EQU     25
+
+; PIO Minimum Active Times (t2)
+PIO_0_MIN_ACTIVE_TIME_NS    EQU     165
+PIO_1_MIN_ACTIVE_TIME_NS    EQU     125
+PIO_2_MIN_ACTIVE_TIME_NS    EQU     100
+PIO_3_MIN_ACTIVE_TIME_NS    EQU     80
+PIO_4_MIN_ACTIVE_TIME_NS    EQU     70
+
+; PIO Minimum Recovery Times or Inactive Times (t2i) can be calculated
+; from Minimum Cycle Time (t0) - Minimum Active Time (t2) - Address Valid Time (t1). 
+; I'm not sure about this calculation so correct me if I'm wrong!
+; Recovery time should be calculated at run time since Cycle Time t0 can be
+; read from ATA information (ATA2+) but most drives just report the
+; Min Cycle Times listed above.
+
+
 
 ; ATA-1 Drive Information struct
@@ -32 +63 @@
                 resw 1  ; 50R
                 resb 1  ; 51[0-7]X
-    .bPIOTiming resb 1  ; 51[8-15]F, PIO data transfer cycle timing mode
+    .bPioMode   resb 1  ; 51[8-15]F, PIO data transfer cycle timing mode (0, 1 or 2)
                 resb 1  ; 52[0-7]X
     .bDMATiming resb 1  ; 52[8-15]F, DMA data transfer cycle timing mode
@@ -163 +194 @@
 A2_bBlockFlgs_VALID     EQU (1<<0)  ; Multiple sector setting (bBlockSel) is valid
 
+; ATA-2 Word 64, Advanced PIO transfer modes supported
+A2_bPIOSupp_PIO3        EQU (1<<0)
+A2_bPIOSupp_PIO4        EQU (1<<1)
+
 
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