Changeset 622 in xtideuniversalbios


Ignore:
Timestamp:
Dec 16, 2021, 5:46:51 PM (5 weeks ago)
Author:
aitotat
Message:
  • Supported VLB controllers are now forced to 32-bit mode on 386 builds only. AT builds use 16-bit transfers unless configured to 32-bit from xtidecfg
  • Partially fixed support for PDC 20230C VLB IDE controller. PIO-1 drives stay at PIO-0 but PIO-2, 3 and 4 drives are set to maximum speed that PDC2030C supports
  • Large 386 build is now 12k instead of 10k (did not fit to 10k because of the fixes)
Location:
trunk/XTIDE_Universal_BIOS
Files:
5 edited

Legend:

Unmodified
Added
Removed
  • trunk/XTIDE_Universal_BIOS/Inc/Controllers/PDC20x30.inc

    r589 r622  
    2222%define PDC20x30_INC
    2323
     24;
    2425
    25 ; SECTOR_COUNT_REGISTER in programming mode
    26 FLG_PDCSCR_UNKNOWN_BIT7     EQU     (1<<7)  ; Set to 1 for speed setting 7 of device 0 or 1
    27 FLG_PDCSCR_ID3              EQU     (1<<6)  ; VLB bus speed: 0 > 33 MHz, 1 <= 33 MHz
    28 POS_PDCSCR_DEV0SPEED        EQU     3
    29 MASK_PDCSCR_DEV0SPEED       EQU     (7<<POS_PDCSCR_DEV0SPEED)   ; 0 to 7
    30 MASK_PDCSCR_DEV1SPEED       EQU     (7<<0)                      ; 0 to 7
     26; SECTOR_COUNT_REGISTER (1F2) in programming mode
     27FLG_PDCSCR_BOTHMAX          EQU     (1<<6)  ; Master and Slave at maximum speed
     28
     29; SECTOR_NUMBER_REGISTER (1F3) in programming mode
     30FLG_PDCSNR_UNKNOWN_BIT7     EQU     (1<<7)  ; Set to 1 for speed setting 7 of device 0 or 1
     31FLG_PDCSNR_ID3              EQU     (1<<6)  ; VLB bus speed: 0 > 33 MHz, 1 <= 33 MHz
     32POS_PDCSNR_DEV0SPEED        EQU     3
     33MASK_PDCSNR_DEV0SPEED       EQU     (7<<POS_PDCSNR_DEV0SPEED)   ; 0 to 7
     34MASK_PDCSNR_DEV1SPEED       EQU     (7<<0)                      ; 0 to 7
     35
     36; Disassembly of VG4.BIN: (might have errors)
     37; FLG_PDCSNR_UNKNOWN_BIT7 will be set if no dev1, no matter what speed
     38; FLG_PDCSNR_UNKNOWN_BIT7 will be cleared if dev1 found but no master
     39; FLG_PDCSNR_UNKNOWN_BIT7 will be cleared if dev0 and dev1 speeds are both 7 !
     40; FLG_PDCSNR_UNKNOWN_BIT7 will be cleared if dev 1 is 7 !
     41; If dev 1 is 6 or less and dev 0 is 7, then dev0-- and set FLG_PDCSCR_UNKNOWN_BIT7
     42;
     43
    3144
    3245
     
    3649FLG_PDCLCR_DEV1SPEED_BIT4   EQU     (1<<6)  ; Same as above but for device 1
    3750FLG_PDCLCR_DEV0IORDY        EQU     (1<<5)  ; Not sure about this
    38 FLG_PDCLCR_DEV1IORDY        EQU     (1<<4)  ; Same as above but for device 15
     51FLG_PDCLCR_DEV1IORDY        EQU     (1<<4)  ; Same as above but for device 1
    3952FLG_PDCLCR_ENABLE_EXTRA_REGISTERS   EQU (1<<3)
    4053
  • trunk/XTIDE_Universal_BIOS/Src/Device/IDE/IdeDPT.asm

    r618 r622  
    135135    ; We have detected 32-bit controller so change Device Type since
    136136    ; it might have been set to 16-bit on IDEVARS
     137    ;
     138    ; Change to 32-bit on 386 builds only. We leave AT builds unchanged for faster troubleshooting
     139    ; and for uncommon systems, like IBM 486SLC2 processors that can have VLB motherboard even though
     140    ; the IBM 486SLC2 is externally 16-bit CPU
    137141.ChangeTo32bitDevice:
     142%ifdef USE_386
    138143    mov     BYTE [di+DPT_ATA.bDevice], DEVICE_32BIT_ATA
     144%endif
    139145.NoAdvancedControllerDetected:
    140146%endif  ; MODULE_ADVANCED_ATA
    141147
    142 
    143 ; End DPT
     148    ; End DPT
    144149    clc
    145150    ret
  • trunk/XTIDE_Universal_BIOS/Src/Initialization/AdvancedAta/AdvAtaInit.asm

    r601 r622  
    182182.PioTimingsLoadedToBXandCX:
    183183    ret
     184
     185
     186;--------------------------------------------------------------------
     187; Just a simple IN AL, DX instruction but the function call works
     188; as I/O delay.
     189;
     190; AdvAtaInit_InWithDelay
     191;   Parameters:
     192;       DX:     Port to read from
     193;   Returns:
     194;       AL:     Byte read from port
     195;   Corrupts registers:
     196;       Nothing
     197;--------------------------------------------------------------------   
     198AdvAtaInit_InputWithDelay:
     199    in      al, dx
     200    ret
  • trunk/XTIDE_Universal_BIOS/Src/Initialization/AdvancedAta/PDC20x30.asm

    r592 r622  
    5353;--------------------------------------------------------------------
    5454GetPdcIDtoAX:
     55;Force ID_PDC20230 instead of PDC20630 detection
     56;mov    ax, ID_PDC20230<<8
     57;jmp        SHORT DisablePdcProgrammingMode
     58
    5559    push    dx
    5660
     
    8791;--------------------------------------------------------------------
    8892DisablePdcProgrammingMode:
    89     add     dx, BYTE HIGH_CYLINDER_REGISTER
     93    add     dx, BYTE HIGH_CYLINDER_REGISTER ; 1F5h
    9094    in      al, dx
    9195    add     dx, -HIGH_CYLINDER_REGISTER     ; Sets CF for PDC20x30_DetectControllerForIdeBaseInBX
     96%if 0
     97    ; Disassembly of VG4.BIN shows that bit 7 (programming mode activated)
     98    ; is cleared manually after reading from HIGH_CYLINDER_REGISTER
     99    ; That does not seem to be necessary.
     100    inc     dx
     101    inc     dx
     102    call    AdvAtaInit_InputWithDelay
     103    and     al, 7Fh
     104    out     dx, al
     105    dec     dx
     106    dec     dx
     107    stc
     108%endif
    92109.Return:
    93110    ret
     
    108125    inc     dx
    109126    inc     dx
    110     in      al, dx  ; 1F2h (SECTOR_COUNT_REGISTER)
     127    call    AdvAtaInit_InputWithDelay   ; 1F2h (SECTOR_COUNT_REGISTER)
    111128    or      al, 80h
    112129    out     dx, al
    113130
    114     ; PDC detection sequence (should delay be added between register reads?)
    115     add     dx, BYTE HIGH_CYLINDER_REGISTER - SECTOR_COUNT_REGISTER
    116     in      al, dx  ; 1F5h
     131    ; PDC detection sequence
     132    add     dx, BYTE HIGH_CYLINDER_REGISTER - SECTOR_COUNT_REGISTER ; 5 - 2
    117133    cli
     134    call    AdvAtaInit_InputWithDelay   ; 1F5
     135
    118136    sub     dx, BYTE HIGH_CYLINDER_REGISTER - SECTOR_COUNT_REGISTER
    119     in      al, dx  ; 1F2h
    120     add     dx, STANDARD_CONTROL_BLOCK_OFFSET + (ALTERNATE_STATUS_REGISTER_in - SECTOR_COUNT_REGISTER)
    121     in      al, dx  ; 3F6h
    122     in      al, dx  ; 3F6h
     137    call    AdvAtaInit_InputWithDelay   ; 1F2h
     138
     139    add     dx, STANDARD_CONTROL_BLOCK_OFFSET + (ALTERNATE_STATUS_REGISTER_in - SECTOR_COUNT_REGISTER)  ; 200h+(6-2)
     140    call    AdvAtaInit_InputWithDelay   ; 3F6h
     141
     142    call    AdvAtaInit_InputWithDelay   ; 3F6h
     143
    123144    sub     dx, STANDARD_CONTROL_BLOCK_OFFSET + (ALTERNATE_STATUS_REGISTER_in - SECTOR_COUNT_REGISTER)
    124     in      al, dx  ; 1F2h
    125     in      al, dx  ; 1F2h
     145    call    AdvAtaInit_InputWithDelay   ; 1F2h
     146
     147    call    AdvAtaInit_InputWithDelay   ; 1F2h
    126148    sti
    127149
    128150    ; PDC20230C and PDC20630 clears the bit we set at the beginning
    129     in      al, dx  ; 1F2h
     151    call    AdvAtaInit_InputWithDelay   ; 1F2h
    130152    dec     dx
    131153    dec     dx      ; Base port
     
    186208    jne     SHORT .InitializationCompleted
    187209    call    SetPdc20630SpeedForDriveInCX
     210
     211    ; TODO: Should we first call SetPdc20630SpeedForDriveInCX and then
     212    ; force SetSpeedForDriveInCX to PIO 0 (maximum speed setting 8)?
     213    ; Need to test with PCD20630.
     214
    188215.InitializationCompleted:
    189216    mov     dx, [di+DPT.wBasePort]
     
    200227;       DS:DI:  Ptr to DPT
    201228;   Returns:
    202 ;       DX:     Sector Number Register
     229;       DX:     Sector Number Register (1F3h)
    203230;   Corrupts registers:
    204231;       AX, BX
     
    211238    xchg    bx, ax
    212239
    213     add     dx, BYTE SECTOR_NUMBER_REGISTER
    214     mov     bh, ~MASK_PDCSCR_DEV1SPEED  ; Assume slave
     240    add     dx, BYTE SECTOR_NUMBER_REGISTER ; 1F3h
     241    mov     bh, ~MASK_PDCSNR_DEV1SPEED      ; Assume slave
    215242    inc     cx
     243    mov     ah, 7   ; Max speed value. Set unknown bit 7 if either of drives are set to this
    216244    loop    .SetSpeed
    217     eSHL_IM bl, POS_PDCSCR_DEV0SPEED
    218     mov     bh, ~MASK_PDCSCR_DEV0SPEED
     245    mov     ah, 7 << POS_PDCSNR_DEV0SPEED
     246    eSHL_IM bl, POS_PDCSNR_DEV0SPEED
     247    mov     bh, ~MASK_PDCSNR_DEV0SPEED
    219248.SetSpeed:
    220249    in      al, dx
    221250    and     al, bh
    222251    or      al, bl
    223     cmp     bl, 7
     252    cmp     bl, ah
    224253    jb      SHORT .OutputNewValue
    225     or      al, FLG_PDCSCR_UNKNOWN_BIT7 ; Flag for PIO 2 and above?
     254    or      al, FLG_PDCSNR_UNKNOWN_BIT7     ; Flag for PIO 2 and above?
    226255.OutputNewValue:
    227256    out     dx, al
     257
     258    ; The above speed set does not work with Octek VL-COMBO rev 3.2 with PDC20230C
     259    ; Only thing to make it work is to set FLG_PDCSCR_BOTHMAX to 1F2h. Are all PDC20230C controllers
     260    ; like that? If so, why the above speed is not set? Or does the VL-COMBO or other PDC20230C
     261    ; controllers have a jumper to prevent speed setup by software? (PDC20230B can only be set
     262    ; by hardware, for example), like pin-compatible operation with older PDC20230B, perhaps?
     263    ; Datasheets would be very useful...
     264    ; For now, we just set the FLG_PDCSCR_BOTHMAX bit if either of the drives are set to speed 7
     265    ;
     266    ; Code below is not perfect. It does not properly test if both drives support PIO 2 but
     267    ; likely if slave does, so does master (and if slave does not, we clear the
     268    ; FLG_PDCSCR_BOTHMAX set by master)
     269    mov     bl, 1   ; Set bit 0, see VG4.BIN comments below
     270    test    al, al
     271    jns     SHORT .DoNotSetMaxSpeedBit
     272    or      bl, FLG_PDCSCR_BOTHMAX
     273.DoNotSetMaxSpeedBit:
     274    dec     dx      ; SECTOR_COUNT_REGISTER, 1F2h
     275    call    AdvAtaInit_InputWithDelay
     276    and     al, ~FLG_PDCSCR_BOTHMAX
     277    or      al, bl
     278    out     dx, al
     279
     280    ; VG4.BIN ("External BIOS") does the following after programming speed (1F3h)
     281    ; (It never seems to set the speed bit we just set above).
     282    ; The below code does not seem to have any effect, at least not for PDC20230C.
     283    ; Why is bit 0 set to 1F2h?
     284    ; Is it just to keep programming mode active if it has timeout, for example?
     285    ; But after all that it just reads 1F5h to disable programming mode.
     286%if 0
     287    ; Test code start
     288    push    cx
     289    mov     cx, 100
     290    DELAY_WITH_LOOP_INSTRUCTION_NA
     291
     292    ; Does below tell the controller that new speed is set?
     293    in      al, dx
     294    or      al, 1
     295    out     dx, al
     296
     297    mov     cx, 100
     298    DELAY_WITH_LOOP_INSTRUCTION_NA
     299    pop     cx
     300    ; Test code end
     301%endif
     302
     303    inc     dx      ; SECTOR_NUMBER_REGISTER, 1F3h
    228304    ret
    229305
     
    239315;       CX:     0 for master, 1 for slave drive
    240316;       DS:DI:  Ptr to DPT
    241 ;       DX:     Sector Number Register
     317;       DX:     Sector Number Register, 1F3h
    242318;   Returns:
    243319;       DX:     Low Cylinder Register
  • trunk/XTIDE_Universal_BIOS/makefile

    r621 r622  
    134134BIOS_SIZE_TINY = 4096
    135135BIOS_SIZE_SMALL = 8192
    136 BIOS_SIZE_LARGE = 10240
     136BIOS_SIZE_LARGE = 12288
    137137BIOS_SIZE_CUSTOM = ?
    138138
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