source: xtideuniversalbios/trunk/XTIDE_Universal_BIOS/Inc/Controllers/PDC20x30.inc @ 622

Last change on this file since 622 was 622, checked in by aitotat, 2 years ago
  • Supported VLB controllers are now forced to 32-bit mode on 386 builds only. AT builds use 16-bit transfers unless configured to 32-bit from xtidecfg
  • Partially fixed support for PDC 20230C VLB IDE controller. PIO-1 drives stay at PIO-0 but PIO-2, 3 and 4 drives are set to maximum speed that PDC2030C supports
  • Large 386 build is now 12k instead of 10k (did not fit to 10k because of the fixes)
File size: 2.7 KB
Line 
1; Project name  :   XTIDE Universal BIOS
2; Description   :   Promise PDC 20230-C and 20630 VLB IDE controller
3;                   specifications.
4
5;
6; XTIDE Universal BIOS and Associated Tools
7; Copyright (C) 2009-2010 by Tomi Tilli, 2011-2013 by XTIDE Universal BIOS Team.
8;
9; This program is free software; you can redistribute it and/or modify
10; it under the terms of the GNU General Public License as published by
11; the Free Software Foundation; either version 2 of the License, or
12; (at your option) any later version.
13;
14; This program is distributed in the hope that it will be useful,
15; but WITHOUT ANY WARRANTY; without even the implied warranty of
16; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17; GNU General Public License for more details.
18; Visit http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
19;
20
21%ifndef PDC20x30_INC
22%define PDC20x30_INC
23
24;
25
26; SECTOR_COUNT_REGISTER (1F2) in programming mode
27FLG_PDCSCR_BOTHMAX          EQU     (1<<6)  ; Master and Slave at maximum speed
28
29; SECTOR_NUMBER_REGISTER (1F3) in programming mode
30FLG_PDCSNR_UNKNOWN_BIT7     EQU     (1<<7)  ; Set to 1 for speed setting 7 of device 0 or 1
31FLG_PDCSNR_ID3              EQU     (1<<6)  ; VLB bus speed: 0 > 33 MHz, 1 <= 33 MHz
32POS_PDCSNR_DEV0SPEED        EQU     3
33MASK_PDCSNR_DEV0SPEED       EQU     (7<<POS_PDCSNR_DEV0SPEED)   ; 0 to 7
34MASK_PDCSNR_DEV1SPEED       EQU     (7<<0)                      ; 0 to 7
35
36; Disassembly of VG4.BIN: (might have errors)
37; FLG_PDCSNR_UNKNOWN_BIT7 will be set if no dev1, no matter what speed
38; FLG_PDCSNR_UNKNOWN_BIT7 will be cleared if dev1 found but no master
39; FLG_PDCSNR_UNKNOWN_BIT7 will be cleared if dev0 and dev1 speeds are both 7 !
40; FLG_PDCSNR_UNKNOWN_BIT7 will be cleared if dev 1 is 7 !
41; If dev 1 is 6 or less and dev 0 is 7, then dev0-- and set FLG_PDCSCR_UNKNOWN_BIT7
42;
43
44
45
46; LOW_CYLINDER_REGISTER in programming mode
47; This is only on PDC 20630!
48FLG_PDCLCR_DEV0SPEED_BIT4   EQU     (1<<7)  ; Possibly speed bit 4 (speed settings 8 to 15)?
49FLG_PDCLCR_DEV1SPEED_BIT4   EQU     (1<<6)  ; Same as above but for device 1
50FLG_PDCLCR_DEV0IORDY        EQU     (1<<5)  ; Not sure about this
51FLG_PDCLCR_DEV1IORDY        EQU     (1<<4)  ; Same as above but for device 1
52FLG_PDCLCR_ENABLE_EXTRA_REGISTERS   EQU (1<<3)
53
54
55; PDC 20630 specific registers mapped after IDE registers
56PDC20630_INDEX_REGISTER     EQU     8       ; 1F8h
57PDC20630_DATA_REGISTER      EQU     9       ; 1F9h
58
59; PDC 20630 registers to access through index and data register
60PDCREG0_TIMING_OF_DEV0_LOW  EQU     0       ; Low, high, what timings?
61PDCREG1_TIMING_OF_DEV0_HIGH EQU     1
62PDCREG2_TIMING_OF_DEV1_LOW  EQU     2
63PDCREG3_TIMING_OF_DEV1_HIGH EQU     3
64PDCREG7_STATUS              EQU     7
65
66FLG_PDCSTATUS_DMA_ERROR             EQU (1<<4)  ; ?
67FLG_PDCSTATUS_DMA_READ_COMPLETED    EQU (1<<1)  ; ?
68FLG_PDCSTATUS_DMA_WRITE_COMPLETED   EQU (1<<0)  ; ?
69
70
71%endif ; PDC20x30_INC
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