Changeset 545 in xtideuniversalbios for trunk/XTIDE_Universal_BIOS/Inc/Controllers


Ignore:
Timestamp:
Apr 19, 2013, 11:44:35 AM (12 years ago)
Author:
aitotat@…
google:author:
aitotat@gmail.com
Message:

Changes to XTIDE Universal BIOS:

  • Integrated XT-CFv3 support by James Pearce.
  • XT-CFv2 memory mapped I/O and DMA modes are no longer supported (but PIO mode is).
File:
1 edited

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  • trunk/XTIDE_Universal_BIOS/Inc/Controllers/XTCF.inc

    r526 r545  
    22; Description   :   Lo-tech XT-CFv2 board specifications.
    33;
    4 ;                   More information at http://www.lo-tech.co.uk/wiki/Lo-tech_XT-CFv2_Board
     4; More information at http://www.lo-tech.co.uk/XT-CF
    55
    66;
    … …  
    2020;
    2121
     22; Modified by JJP for XT-CFv3 support, Mar-13
     23
     24
    2225%ifndef XTCF_INC
    2326%define XTCF_INC
    2427
    25 DEFAULT_XTCF_SECTOR_WINDOW_SEGMENT  EQU     0D800h
    26 
    27 ; XT-CF requires that block must be less than 128 sectors (64 kiB).
    28 ; Instead of limiting block size to 64, we limit it to 32 (16 kiB).
    29 ; Transferring more than 16 kiB with 8237 DMA controller block or demand
    30 ; mode might interfere with DRAM refresh on XT systems.
    31 XTCF_DMA_MODE_MAX_BLOCK_SIZE        EQU     32      ; Sectors
     28; XT-CF requires that block must be less than 128 sectors (64 kiB) for DMA
     29; transfers.
     30;
     31; Note: XT-CFv3 DMA will not interfere with PC & PC/XT memory refresh,
     32; since the XT-CFv3 detaches itself from the bus every 16 bytes transferred.
     33;
     34XTCF_DMA_MODE_MAX_BLOCK_SIZE        EQU     64      ; Sectors
    3235
    3336; Possible base addresses. Note that all XT-CF IDE registers are SHL 1 compared
    3437; to standard IDE registers.
    35 XTCF_BASE_PORT_DETECTION_SEED       EQU     140h    ; Not a valid base address but needed for autodetection
    3638XTCF_BASE_PORT_1                    EQU     200h
    3739XTCF_BASE_PORT_2                    EQU     240h
    … …  
    4143
    4244; XT-CF Control Register (do not SHL 1 these!)
    43 XTCF_CONTROL_REGISTER               EQU     1Fh
    44 XTCF_CONTROL_REGISTER_INVERTED_in   EQU     1Eh
     45; Note: XT-CFv3 control register is used *only* to raise DRQ.  The register cannot be read.
     46;
     47XTCF_CONTROL_REGISTER               EQU     1Eh
    4548
    46 ; Control Register contents:
     49; Transfer Mode Constants
    4750;
    48 ; Control Register holds high byte from Sector Window segment if >= A0h
    49 ; (First possible segment for Sector Window is A000h)
     51; Available transfer modes depend on the controller.  All XT-CF controllers
     52; support 8-bit PIO, either with 8-bit or 16-bit instructions (i.e., data
     53; can be fetched from the controller with REP INSW or REP INSB since A0 is
     54; not decoded).  However, errors in the implementation of the BIU on some
     55; machines will prevent 16-bit instructions delivering data correctly.
    5056;
    51 ; 8-bit PIO transfers (port I/O) are used if Control Register is zero.
    52 ; Any other value means DMA transfers (using DMA channel 3).
    53 XTCF_8BIT_PIO_MODE                      EQU     0
    54 XTCF_DMA_MODE                           EQU     10h
    55 XTCF_MEMORY_MAPPED_MODE                 EQU     0A0h
    56 RAISE_DRQ_AND_CLEAR_XTCF_XFER_COUNTER   EQU     40h
    57 
    58 
     57; For XT-CFv3 adapter, DMA transfers are also supported via channel 3.
     58;
     59; XT-CFv3 cannot be distinguised by software, so user must decide and set
     60; the mode via a call to Int 13h function 1Eh accordingly (see AH1E_XTCF.asm).
     61;;
     62XTCF_8BIT_PIO_MODE                  EQU     00h
     63XTCF_8BIT_PIO_MODE_WITH_BIU_OFFLOAD EQU     01h
     64XTCF_DMA_MODE                       EQU     02h
    5965
    6066; Subcommands for AH=1Eh, Lo-tech XT-CF features.
    … …  
    7278
    7379;--------------------------------------------------------------------
    74 ; READ_XTCF_CONTROL_REGISTER_TO_DH
     80; SET_XTCF_TRANSFER_MODE
     81;   Parameters:
     82;       DH:     Mode to select,
     83;                               i.e. XTCF_8BIT_PIO_MODE
     84;               Note there's no way to know if an
     85;               XT-CF adapter supports DMA, so the
     86;               user should enable DMA only if a
     87;               DMA-enabled XT-CFv3 is fitted.
     88;       DL:     Drive Number
     89;--------------------------------------------------------------------
     90SET_XTCF_TRANSFER_MODE              EQU     1
     91
     92;--------------------------------------------------------------------
     93; GET_XTCF_TRANSFER_MODE
    7594;   Parameters:
    7695;       DL:     Drive Number
    7796;   Returns:
    78 ;       DH:     XT-CF Control Register contents
     97;       DL:     Block mode sectors per block
     98;               configured
     99;       DH:     One of the mode values listed above,
     100;                               i.e. XTCF_8BIT_PIO_MODE
    79101;--------------------------------------------------------------------
    80 READ_XTCF_CONTROL_REGISTER_TO_DH    EQU     1
    81 
    82 ;--------------------------------------------------------------------
    83 ; WRITE_DH_TO_XTCF_CONTROL_REGISTER
    84 ;   Parameters:
    85 ;       DH:     Byte to write to XT-CF Control Register
    86 ;       DL:     Drive Number
    87 ;--------------------------------------------------------------------
    88 WRITE_DH_TO_XTCF_CONTROL_REGISTER   EQU     2
     102GET_XTCF_TRANSFER_MODE              EQU     2
    89103
    90104
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