Changeset 473 in xtideuniversalbios for trunk/XTIDE_Universal_BIOS/Src/Device/IDE/IdeIO.asm
- Timestamp:
- Oct 10, 2012, 6:22:23 PM (12 years ago)
- google:author:
- aitotat@gmail.com
- File:
-
- 1 edited
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trunk/XTIDE_Universal_BIOS/Src/Device/IDE/IdeIO.asm
r443 r473 1 1 ; Project name : XTIDE Universal BIOS 2 ; Description : IDE Register I/O functions. 2 ; Description : IDE Register I/O functions when supporting 8-bit 3 ; devices that need address translations. 3 4 4 5 ; … … 22 23 23 24 ;-------------------------------------------------------------------- 25 ; IdeIO_InputStatusRegisterToAL 26 ; Parameters: 27 ; DS:DI: Ptr to DPT (in RAMVARS segment) 28 ; Returns: 29 ; AL: IDE Status Register contents 30 ; Corrupts registers: 31 ; BX, DX 32 ;-------------------------------------------------------------------- 33 ALIGN JUMP_ALIGN 34 IdeIO_InputStatusRegisterToAL: 35 %ifndef MODULE_8BIT_IDE 36 INPUT_TO_AL_FROM_IDE_REGISTER STATUS_REGISTER_in 37 ret 38 39 %else 40 mov dl, STATUS_REGISTER_in 41 ; Fall to IdeIO_InputToALfromIdeRegisterInDL 42 43 ;-------------------------------------------------------------------- 44 ; IdeIO_InputToALfromIdeRegisterInDL 45 ; Parameters: 46 ; DL: IDE Register 47 ; DS:DI: Ptr to DPT (in RAMVARS segment) 48 ; Returns: 49 ; AL: Inputted byte 50 ; Corrupts registers: 51 ; BX, DX 52 ;-------------------------------------------------------------------- 53 IdeIO_InputToALfromIdeRegisterInDL: 54 xor dh, dh ; IDE Register index now in DX 55 56 mov al, [di+DPT_ATA.bDevice] 57 cmp al, DEVICE_8BIT_XTIDE_REV2 58 je SHORT .ReverseA0andA3fromRegisterIndexInDX 59 jb SHORT .InputToALfromRegisterInDX ; Standard IDE controllers and XTIDE rev 1 60 cmp al, DEVICE_8BIT_JRIDE_ISA 61 jne SHORT .ShlRegisterIndexInDX ; All XT-CF modes 62 ; Fall to .InputToALfromMemoryMappedRegisterInDX 63 64 .InputToALfromMemoryMappedRegisterInDX: 65 mov bx, JRIDE_COMMAND_BLOCK_REGISTER_WINDOW_OFFSET 66 add bx, dx 67 push ds 68 mov ds, [di+DPT.wBasePort] ; Segment for JR-IDE/ISA 69 mov al, [bx] 70 pop ds 71 ret 72 73 .ReverseA0andA3fromRegisterIndexInDX: 74 mov bx, dx 75 mov dl, [cs:bx+g_rgbSwapA0andA3fromIdeRegisterIndex] 76 SKIP2B bx ; Skip shl dx, 1 77 78 .ShlRegisterIndexInDX: 79 shl dx, 1 80 ; Fall to .InputToALfromRegisterInDX 81 82 .InputToALfromRegisterInDX: 83 add dx, [di+DPT.wBasePort] 84 in al, dx 85 ret 86 87 88 ;-------------------------------------------------------------------- 24 89 ; IdeIO_OutputALtoIdeControlBlockRegisterInDL 25 90 ; Parameters: … … 33 98 ;-------------------------------------------------------------------- 34 99 IdeIO_OutputALtoIdeControlBlockRegisterInDL: 35 %ifdef MODULE_8BIT_IDE 36 mov dh, [di+DPT_ATA.bDevice] 37 %ifdef MODULE_JRIDE 38 test dh, dh 39 jnz SHORT .OutputToIoMappedIde 40 41 add dx, JRIDE_CONTROL_BLOCK_REGISTER_WINDOW_OFFSET 42 jmp SHORT OutputToJrIdeRegister 43 .OutputToIoMappedIde: 44 %endif ; MODULE_JRIDE 45 %endif ; MODULE_8BIT_IDE 100 ; Note! We do not need to reverse A0 and A3 for XTIDE rev 2 since 101 ; the only Control Block Register we access is DEVICE_CONTROL_REGISTER_out 102 ; at offset 6 (0110b). 103 xor dh, dh ; IDE Register index now in DX 46 104 47 mov bl, IDEVARS.wPortCtrl 48 jmp SHORT OutputALtoIdeRegisterInDLwithIdevarsOffsetToBasePortInBL 105 mov bl, [di+DPT_ATA.bDevice] 106 cmp bl, DEVICE_8BIT_XTIDE_REV2 107 jbe SHORT .OutputALtoControlBlockRegisterInDX ; Standard IDE controllers and XTIDE rev 1 108 cmp bl, DEVICE_8BIT_JRIDE_ISA 109 jne SHORT .ShlRegisterIndexInDX ; All XT-CF modes 110 ; Fall to .OutputALtoMemoryMappedRegisterInDX 111 112 .OutputALtoMemoryMappedRegisterInDX: 113 mov bx, JRIDE_CONTROL_BLOCK_REGISTER_WINDOW_OFFSET 114 jmp SHORT IdeIO_OutputALtoIdeRegisterInDL.OutputALtoMemoryMappedRegisterInDXwithWindowOffsetInBX 115 116 .ShlRegisterIndexInDX: 117 add dl, OFFSET_TO_CONTROL_BLOCK_REGISTERS 118 shl dx, 1 119 jmp SHORT OutputALtoRegisterInDX 120 121 .OutputALtoControlBlockRegisterInDX: 122 call AccessDPT_GetIdevarsToCSBX 123 add dx, [cs:bx+IDEVARS.wControlBlockPort] 124 jmp SHORT OutputALtoPortInDX 49 125 50 126 … … 62 138 ALIGN JUMP_ALIGN 63 139 IdeIO_OutputALtoIdeRegisterInDL: 64 %ifdef MODULE_8BIT_IDE 65 mov dh, [di+DPT_ATA.bDevice] 66 %ifdef MODULE_JRIDE 67 test dh, dh 68 jnz SHORT OutputALtoIOmappedIdeRegisterInDL 69 70 %if JRIDE_COMMAND_BLOCK_REGISTER_WINDOW_OFFSET & 0FFh = 0 71 mov dh, JRIDE_COMMAND_BLOCK_REGISTER_WINDOW_OFFSET >> 8 72 %else 73 add dx, JRIDE_COMMAND_BLOCK_REGISTER_WINDOW_OFFSET 74 %endif 75 OutputToJrIdeRegister: 76 mov bx, dx 77 mov [cs:bx], al 78 ret 79 ALIGN JUMP_ALIGN 80 OutputALtoIOmappedIdeRegisterInDL: 81 %endif ; MODULE_JRIDE 82 %endif ; MODULE_8BIT_IDE 140 xor dh, dh ; IDE Register index now in DX 83 141 84 mov bl, IDEVARS.wPort 85 OutputALtoIdeRegisterInDLwithIdevarsOffsetToBasePortInBL: 86 call GetIdePortToDX 142 mov bl, [di+DPT_ATA.bDevice] 143 cmp bl, DEVICE_8BIT_XTIDE_REV2 144 je SHORT .ReverseA0andA3fromRegisterIndexInDX 145 jb SHORT OutputALtoRegisterInDX ; Standard IDE controllers and XTIDE rev 1 146 cmp bl, DEVICE_8BIT_JRIDE_ISA 147 jne SHORT .ShlRegisterIndexInDX ; All XT-CF modes 148 ; Fall to .OutputALtoMemoryMappedRegisterInDX 149 150 .OutputALtoMemoryMappedRegisterInDX: 151 mov bx, JRIDE_COMMAND_BLOCK_REGISTER_WINDOW_OFFSET 152 .OutputALtoMemoryMappedRegisterInDXwithWindowOffsetInBX: 153 add bx, dx 154 push ds 155 mov ds, [di+DPT.wBasePort] ; Segment for JR-IDE/ISA 156 mov [bx], al 157 pop ds 158 ret 159 160 .ReverseA0andA3fromRegisterIndexInDX: 161 mov bx, dx 162 mov dl, [cs:bx+g_rgbSwapA0andA3fromIdeRegisterIndex] 163 SKIP2B bx ; Skip shl dx, 1 164 165 .ShlRegisterIndexInDX: 166 shl dx, 1 167 ; Fall to OutputALtoRegisterInDX 168 169 ALIGN JUMP_ALIGN 170 OutputALtoRegisterInDX: 171 add dx, [di+DPT.wBasePort] 172 OutputALtoPortInDX: 87 173 out dx, al 88 174 ret 89 175 90 176 91 ;--------------------------------------------------------------------92 ; IdeIO_InputStatusRegisterToAL93 ; Parameters:94 ; DS:DI: Ptr to DPT (in RAMVARS segment)95 ; Returns:96 ; AL: IDE Status Register contents97 ; Corrupts registers:98 ; BX, DX99 ;--------------------------------------------------------------------100 ALIGN JUMP_ALIGN101 IdeIO_InputStatusRegisterToAL:102 mov dl, STATUS_REGISTER_in103 ; Fall to IdeIO_InputToALfromIdeRegisterInDL104 177 105 ;-------------------------------------------------------------------- 106 ; IdeIO_InputToALfromIdeRegisterInDL 107 ; Parameters: 108 ; DL: IDE Register 109 ; DS:DI: Ptr to DPT (in RAMVARS segment) 110 ; Returns: 111 ; AL: Inputted byte 112 ; Corrupts registers: 113 ; BX, DX 114 ;-------------------------------------------------------------------- 115 IdeIO_InputToALfromIdeRegisterInDL: 116 %ifdef MODULE_8BIT_IDE 117 mov dh, [di+DPT_ATA.bDevice] 118 %ifdef MODULE_JRIDE 119 test dh, dh 120 jnz SHORT .InputToALfromIOmappedIdeRegisterInDL 121 122 %if JRIDE_COMMAND_BLOCK_REGISTER_WINDOW_OFFSET & 0FFh = 0 123 mov dh, JRIDE_COMMAND_BLOCK_REGISTER_WINDOW_OFFSET >> 8 124 %else 125 add dx, JRIDE_COMMAND_BLOCK_REGISTER_WINDOW_OFFSET 126 %endif 127 mov bx, dx 128 mov al, [cs:bx] 129 ret 130 .InputToALfromIOmappedIdeRegisterInDL: 131 %endif ; MODULE_JRIDE 132 %endif ; MODULE_8BIT_IDE 133 mov bl, IDEVARS.wPort 134 call GetIdePortToDX 135 in al, dx 136 ret 178 ; A0 <-> A3 lookup table 179 g_rgbSwapA0andA3fromIdeRegisterIndex: 180 db 0000b ; <-> 0000b, 0 181 db 1000b ; <-> 0001b, 1 182 db 0010b ; <-> 0010b, 2 183 db 1010b ; <-> 0011b, 3 184 db 0100b ; <-> 0100b, 4 185 db 1100b ; <-> 0101b, 5 186 db 0110b ; <-> 0110b, 6 187 db 1110b ; <-> 0111b, 7 137 188 138 139 ;-------------------------------------------------------------------- 140 ; GetIdePortToDX 141 ; Parameters: 142 ; BL: Offset to port in IDEVARS (IDEVARS.wPort or IDEVARS.wPortCtrl) 143 ; DH: Device Type (IDEVARS.bDevice) 144 ; DL: IDE Register 145 ; DS:DI: Ptr to DPT (in RAMVARS segment) 146 ; Returns: 147 ; DX: Source/Destination Port 148 ; Corrupts registers: 149 ; BX 150 ;-------------------------------------------------------------------- 151 ALIGN JUMP_ALIGN 152 GetIdePortToDX: 153 %ifdef MODULE_8BIT_IDE 154 ; Point CS:BX to IDEVARS 155 xor bh, bh 156 add bl, [di+DPT.bIdevarsOffset] ; CS:BX now points port address 157 158 ; Load port address and check if A0 and A3 address lines need to be reversed 159 cmp dh, DEVICE_8BIT_XTIDE_REV1 160 mov dh, bh ; DX now has IDE register offset 161 jae SHORT .ReturnUntranslatedPortInDX ; No need to swap address lines 162 163 ; Exchange address lines A0 and A3 from DL 164 add dx, [cs:bx] ; DX now has port address 165 mov bl, dl ; Port low byte to BL 166 and bl, MASK_A3_AND_A0_ADDRESS_LINES ; Clear all bits except A0 and A3 167 jz SHORT .ReturnTranslatedPortInDX ; A0 and A3 both zeroes, no change needed 168 cmp bl, MASK_A3_AND_A0_ADDRESS_LINES 169 je SHORT .ReturnTranslatedPortInDX ; A0 and A3 both ones, no change needed 170 xor dl, MASK_A3_AND_A0_ADDRESS_LINES ; Invert A0 and A3 171 .ReturnTranslatedPortInDX: 172 ret 173 174 .ReturnUntranslatedPortInDX: 175 add dx, [cs:bx] 176 ret 177 178 %else ; Only standard IDE devices 179 xor bh, bh 180 add bl, [di+DPT.bIdevarsOffset] ; CS:BX now points port address 181 xor dh, dh 182 add dx, [cs:bx] ; DX now has port address 183 ret 184 %endif 189 %endif ; MODULE_8BIT_IDE
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