Changeset 399 in xtideuniversalbios for trunk/XTIDE_Universal_BIOS/Inc


Ignore:
Timestamp:
Apr 19, 2012, 10:39:44 PM (13 years ago)
Author:
krille_n_@…
google:author:
krille_n_@hotmail.com
Message:

Changes:

  • Added Power Management (Standby Timer) support to the BIOS and made it part of an optional module (MODULE_FEATURE_SETS). The total amount of ROM space used by this feature is 37 bytes. UNTESTED
  • Size optimizations (mostly inlining of procedures) and fixed a few bugs in AH9h_HInit.asm:
    1. DPT_ATA.bInitError would be cleared only if MODULE_SERIAL was not defined.
    2. The FLG_INITERROR_FAILED_TO_SET_BLOCK_MODE flag could never be set.
    3. InitializeBlockMode could potentially loop forever if there was an error.
  • Removed some odd looking code in .PushResetStatus in BootMenuPrintCfg.asm
  • Made some changes to XTIDECFG so it can be built.
File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/XTIDE_Universal_BIOS/Inc/CustomDPT.inc

    r397 r399  
    44
    55;
    6 ; XTIDE Universal BIOS and Associated Tools 
     6; XTIDE Universal BIOS and Associated Tools
    77; Copyright (C) 2009-2010 by Tomi Tilli, 2011-2012 by XTIDE Universal BIOS Team.
    88;
     
    1111; the Free Software Foundation; either version 2 of the License, or
    1212; (at your option) any later version.
    13 ; 
     13;
    1414; This program is distributed in the hope that it will be useful,
    1515; but WITHOUT ANY WARRANTY; without even the implied warranty of
    1616; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17 ; GNU General Public License for more details.     
     17; GNU General Public License for more details.
    1818; Visit http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
    1919;
     
    2626    ; General Disk Parameter Table related
    2727    .wFlags:
    28     .bFlagsLow                  resb    1
    29     .bFlagsHigh                 resb    1
    30     .bIdevarsOffset             resb    1   ; Offset to IDEVARS for this drive
     28    .bFlagsLow              resb    1
     29    .bFlagsHigh             resb    1
     30    .bIdevarsOffset         resb    1   ; Offset to IDEVARS for this drive
    3131
    3232    ; IDE Drive related
    3333    ; .bLbaHeads and .twLbaSectors are used for LBA addressing only.
    34     .bLbaHeads:                 resb    1   ; Number of LBA assisted heads (1...255)
    35     .twLbaSectors               resb    2   ; 48-bit sector count for LBA addressing
     34    .bLbaHeads:             resb    1   ; Number of LBA assisted heads (1...255)
     35    .twLbaSectors           resb    2   ; 48-bit sector count for LBA addressing
    3636
    3737    ; .wPchsCylinders and .bPchsSectors are used for CHS addressing only.
    38     .wPchsCylinders             resb    2   ; Number of P-CHS Cylinders (1...16383)
     38    .wPchsCylinders         resb    2   ; Number of P-CHS Cylinders (1...16383)
    3939    .wPchsHeadsAndSectors:
    40     .bPchsHeads                 resb    1   ; Number of P-CHS heads (1...16)
    41     .bPchsSectors               resb    1   ; Number of P-CHS Sectors per Track (1...63)
     40    .bPchsHeads             resb    1   ; Number of P-CHS heads (1...16)
     41    .bPchsSectors           resb    1   ; Number of P-CHS Sectors per Track (1...63)
    4242endstruc
    4343
    44 ; Bit definitions for DPT.bFlagsLow
    45 MASKL_DPT_CHS_SHIFT_COUNT       EQU (7<<0)  ; Bits 0...3, P-CHS to L-CHS bit shift count (0...4)
    46 FLGL_DPT_SLAVE                  EQU FLG_DRVNHEAD_DRV    ; (1<<4), Drive is slave drive
    47 MASKL_DPT_ADDRESSING_MODE       EQU (3<<5)  ; Bits 5..6, Addressing Mode (bit 6 == FLG_DRVNHEAD_LBA)
    48 FLGL_DPT_ENABLE_IRQ             EQU (1<<7)
     44    ; Bit definitions for DPT.bFlagsLow
     45    MASKL_DPT_CHS_SHIFT_COUNT                   EQU (7<<0)  ; Bits 0...2, P-CHS to L-CHS bit shift count (0...4)
     46    FLGL_DPT_SLAVE                              EQU FLG_DRVNHEAD_DRV    ; (1<<4), Drive is slave drive
     47    MASKL_DPT_ADDRESSING_MODE                   EQU (3<<5)  ; Bits 5..6, Addressing Mode (bit 6 == FLG_DRVNHEAD_LBA)
     48    FLGL_DPT_ENABLE_IRQ                         EQU (1<<7)
    4949
    50 ; Bit definitions for DPT.bFlagsHigh
    51 FLGH_DPT_REVERSED_A0_AND_A3     EQU (1<<0)  ; XTIDE mod, Address lines 0 and 3 reversed
    52 FLGH_DPT_BLOCK_MODE_SUPPORTED   EQU (1<<1)  ; Use block transfer commands (must be bit 1!)
    53 %ifdef MODULE_SERIAL
    54 FLGH_DPT_SERIAL_DEVICE          EQU (1<<2)  ; Serial Port Device
    55 %endif
    56 FLGH_DPT_INTERRUPT_IN_SERVICE   EQU (1<<3)  ; Set when waiting for IRQ
     50    ; Bit definitions for DPT.bFlagsHigh
     51    FLGH_DPT_REVERSED_A0_AND_A3                 EQU (1<<0)  ; XTIDE mod, Address lines 0 and 3 reversed
     52    FLGH_DPT_BLOCK_MODE_SUPPORTED               EQU (1<<1)  ; Use block transfer commands (must be bit 1!)
     53    FLGH_DPT_SERIAL_DEVICE                      EQU (1<<2)  ; Serial Port Device
     54    FLGH_DPT_INTERRUPT_IN_SERVICE               EQU (1<<3)  ; Set when waiting for IRQ
     55    FLGH_DPT_POWER_MANAGEMENT_SUPPORTED         EQU (1<<5)
    5756
    58 ; IDE device only
    59 %ifdef MODULE_ADVANCED_ATA
    60 FLGH_DPT_IORDY                  EQU (1<<7)  ; Controller and Drive supports IORDY
    61 %endif
     57    ; IDE device only
     58    FLGH_DPT_IORDY                              EQU (1<<7)  ; Controller and Drive supports IORDY
    6259
    63 ; Serial device only
    64 FLGH_DPT_SERIAL_FLOPPY                      EQU (1<<4)
    65 FLGH_DPT_SERIAL_FLOPPY_TYPE_MASK            EQU 0e0h
    66 FLGH_DPT_SERIAL_FLOPPY_TYPE_FIELD_POSITION  EQU 5
     60    ; Serial device only
     61    FLGH_DPT_SERIAL_FLOPPY                      EQU (1<<4)
     62    FLGH_DPT_SERIAL_FLOPPY_TYPE_MASK            EQU 0e0h
     63    FLGH_DPT_SERIAL_FLOPPY_TYPE_FIELD_POSITION  EQU 5
    6764
    68 ; Addressing modes for DPT.wFlags
    69 ADDRESSING_MODE_FIELD_POSITION  EQU     5
    70 ADDRESSING_MODE_LCHS            EQU     0   ; L-CHS Addressing Mode (NORMAL in many other BIOSes)
    71 ADDRESSING_MODE_PCHS            EQU     1   ; P-CHS Addressing Mode (LARGE in many other BIOSes)
    72 ADDRESSING_MODE_LBA28           EQU     2   ; 28-bit LBA Addressing Mode
    73 ADDRESSING_MODE_LBA48           EQU     3   ; 48-bit LBA Addressing Mode
     65    ; Addressing modes for DPT.wFlags
     66    ADDRESSING_MODE_FIELD_POSITION              EQU     5
     67    ADDRESSING_MODE_LCHS                        EQU     0   ; L-CHS Addressing Mode (NORMAL in many other BIOSes)
     68    ADDRESSING_MODE_PCHS                        EQU     1   ; P-CHS Addressing Mode (LARGE in many other BIOSes)
     69    ADDRESSING_MODE_LBA28                       EQU     2   ; 28-bit LBA Addressing Mode
     70    ADDRESSING_MODE_LBA48                       EQU     3   ; 48-bit LBA Addressing Mode
    7471
    7572
    7673; DPT for ATA devices
    7774struc DPT_ATA   ; 10 + 2 bytes = 12 bytes
    78     .dpt                        resb    DPT_size
    79     .bBlockSize                 resb    1   ; Current block size in sectors (do not set to zero!)
    80     .bInitError                 resb    1
     75    .dpt                    resb    DPT_size
     76    .bBlockSize             resb    1   ; Current block size in sectors (do not set to zero!)
     77    .bInitError             resb    1
    8178endstruc
    8279
    83 ; Flags for DPT_ATA.bInitError
    84 FLG_INITERROR_FAILED_TO_SELECT_DRIVE                EQU     (1<<0)
    85 FLG_INITERROR_FAILED_TO_INITIALIZE_CHS_PARAMETERS   EQU     (1<<1)
    86 FLG_INITERROR_FAILED_TO_SET_WRITE_CACHE             EQU     (1<<2)
    87 FLG_INITERROR_FAILED_TO_RECALIBRATE_DRIVE           EQU     (1<<3)
    88 FLG_INITERROR_FAILED_TO_SET_BLOCK_MODE              EQU     (1<<4)
    89 FLG_INITERROR_FAILED_TO_SET_PIO_MODE                EQU     (1<<5)
    9080
     81    ; Flags for DPT_ATA.bInitError
     82    FLG_INITERROR_FAILED_TO_SELECT_DRIVE                EQU (1<<0)
     83    FLG_INITERROR_FAILED_TO_INITIALIZE_CHS_PARAMETERS   EQU (1<<1)
     84    FLG_INITERROR_FAILED_TO_SET_WRITE_CACHE             EQU (1<<2)
     85    FLG_INITERROR_FAILED_TO_RECALIBRATE_DRIVE           EQU (1<<3)
     86    FLG_INITERROR_FAILED_TO_SET_BLOCK_MODE              EQU (1<<4)
     87    FLG_INITERROR_FAILED_TO_SET_PIO_MODE                EQU (1<<5)
     88    FLG_INITERROR_FAILED_TO_INITIALIZE_STANDBY_TIMER    EQU (1<<6)
    9189
    9290; Additional variables needed to initialize and reset Advanced IDE Controllers.
     
    107105%ifdef MODULE_SERIAL
    108106struc DPT_SERIAL
    109     .dpt                        resb    DPT_size
     107    .dpt                    resb    DPT_size
    110108    .wSerialPortAndBaud:
    111     .bSerialPort                resb    1   ; Serial connection I/O port address, divided by 4
    112     .bSerialBaud                resb    1   ; Serial connection baud rate divisor
     109    .bSerialPort            resb    1   ; Serial connection I/O port address, divided by 4
     110    .bSerialBaud            resb    1   ; Serial connection baud rate divisor
    113111endstruc
    114112%endif
     
    117115; This is the common size for all DPTs. All DPTs must be equal size.
    118116%ifdef MODULE_ADVANCED_ATA
    119 LARGEST_DPT_SIZE                EQU     DPT_ADVANCED_ATA_size
     117    LARGEST_DPT_SIZE            EQU     DPT_ADVANCED_ATA_size
    120118%else
    121 LARGEST_DPT_SIZE                EQU     DPT_ATA_size
     119    LARGEST_DPT_SIZE            EQU     DPT_ATA_size
    122120%endif
    123121
    124122
    125 ; Number of Sectors per Track is fixed to 63 for LBA assist calculation.
    126 ; 1024 cylinders, 256 heads, 63 sectors = 8.4 GB limit (but DOS does not support more than 255 heads)
    127 MAX_LCHS_CYLINDERS              EQU     1024
    128 LBA_ASSIST_SPT                  EQU     63
     123    ; Number of Sectors per Track is fixed to 63 for LBA assist calculation.
     124    ; 1024 cylinders, 256 heads, 63 sectors = 8.4 GB limit (but DOS does not support more than 255 heads)
     125    MAX_LCHS_CYLINDERS          EQU     1024
     126    LBA_ASSIST_SPT              EQU     63
    129127
    130128
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