source: xtideuniversalbios/trunk/XTIDE_Universal_BIOS/Inc/CustomDPT.inc @ 399

Last change on this file since 399 was 399, checked in by krille_n_@…, 12 years ago

Changes:

  • Added Power Management (Standby Timer) support to the BIOS and made it part of an optional module (MODULE_FEATURE_SETS). The total amount of ROM space used by this feature is 37 bytes. UNTESTED
  • Size optimizations (mostly inlining of procedures) and fixed a few bugs in AH9h_HInit.asm:
    1. DPT_ATA.bInitError would be cleared only if MODULE_SERIAL was not defined.
    2. The FLG_INITERROR_FAILED_TO_SET_BLOCK_MODE flag could never be set.
    3. InitializeBlockMode could potentially loop forever if there was an error.
  • Removed some odd looking code in .PushResetStatus in BootMenuPrintCfg.asm
  • Made some changes to XTIDECFG so it can be built.
File size: 5.5 KB
Line 
1; Project name  :   XTIDE Universal BIOS
2; Description   :   Defines for DPT structs containing custom
3;                   Disk Parameter Table used by this BIOS.
4
5;
6; XTIDE Universal BIOS and Associated Tools
7; Copyright (C) 2009-2010 by Tomi Tilli, 2011-2012 by XTIDE Universal BIOS Team.
8;
9; This program is free software; you can redistribute it and/or modify
10; it under the terms of the GNU General Public License as published by
11; the Free Software Foundation; either version 2 of the License, or
12; (at your option) any later version.
13;
14; This program is distributed in the hope that it will be useful,
15; but WITHOUT ANY WARRANTY; without even the implied warranty of
16; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17; GNU General Public License for more details.
18; Visit http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
19;
20
21%ifndef CUSTOMDPT_INC
22%define CUSTOMDPT_INC
23
24; Base DPT for all device types
25struc DPT   ; 10 bytes
26    ; General Disk Parameter Table related
27    .wFlags:
28    .bFlagsLow              resb    1
29    .bFlagsHigh             resb    1
30    .bIdevarsOffset         resb    1   ; Offset to IDEVARS for this drive
31
32    ; IDE Drive related
33    ; .bLbaHeads and .twLbaSectors are used for LBA addressing only.
34    .bLbaHeads:             resb    1   ; Number of LBA assisted heads (1...255)
35    .twLbaSectors           resb    2   ; 48-bit sector count for LBA addressing
36
37    ; .wPchsCylinders and .bPchsSectors are used for CHS addressing only.
38    .wPchsCylinders         resb    2   ; Number of P-CHS Cylinders (1...16383)
39    .wPchsHeadsAndSectors:
40    .bPchsHeads             resb    1   ; Number of P-CHS heads (1...16)
41    .bPchsSectors           resb    1   ; Number of P-CHS Sectors per Track (1...63)
42endstruc
43
44    ; Bit definitions for DPT.bFlagsLow
45    MASKL_DPT_CHS_SHIFT_COUNT                   EQU (7<<0)  ; Bits 0...2, P-CHS to L-CHS bit shift count (0...4)
46    FLGL_DPT_SLAVE                              EQU FLG_DRVNHEAD_DRV    ; (1<<4), Drive is slave drive
47    MASKL_DPT_ADDRESSING_MODE                   EQU (3<<5)  ; Bits 5..6, Addressing Mode (bit 6 == FLG_DRVNHEAD_LBA)
48    FLGL_DPT_ENABLE_IRQ                         EQU (1<<7)
49
50    ; Bit definitions for DPT.bFlagsHigh
51    FLGH_DPT_REVERSED_A0_AND_A3                 EQU (1<<0)  ; XTIDE mod, Address lines 0 and 3 reversed
52    FLGH_DPT_BLOCK_MODE_SUPPORTED               EQU (1<<1)  ; Use block transfer commands (must be bit 1!)
53    FLGH_DPT_SERIAL_DEVICE                      EQU (1<<2)  ; Serial Port Device
54    FLGH_DPT_INTERRUPT_IN_SERVICE               EQU (1<<3)  ; Set when waiting for IRQ
55    FLGH_DPT_POWER_MANAGEMENT_SUPPORTED         EQU (1<<5)
56
57    ; IDE device only
58    FLGH_DPT_IORDY                              EQU (1<<7)  ; Controller and Drive supports IORDY
59
60    ; Serial device only
61    FLGH_DPT_SERIAL_FLOPPY                      EQU (1<<4)
62    FLGH_DPT_SERIAL_FLOPPY_TYPE_MASK            EQU 0e0h
63    FLGH_DPT_SERIAL_FLOPPY_TYPE_FIELD_POSITION  EQU 5
64
65    ; Addressing modes for DPT.wFlags
66    ADDRESSING_MODE_FIELD_POSITION              EQU     5
67    ADDRESSING_MODE_LCHS                        EQU     0   ; L-CHS Addressing Mode (NORMAL in many other BIOSes)
68    ADDRESSING_MODE_PCHS                        EQU     1   ; P-CHS Addressing Mode (LARGE in many other BIOSes)
69    ADDRESSING_MODE_LBA28                       EQU     2   ; 28-bit LBA Addressing Mode
70    ADDRESSING_MODE_LBA48                       EQU     3   ; 48-bit LBA Addressing Mode
71
72
73; DPT for ATA devices
74struc DPT_ATA   ; 10 + 2 bytes = 12 bytes
75    .dpt                    resb    DPT_size
76    .bBlockSize             resb    1   ; Current block size in sectors (do not set to zero!)
77    .bInitError             resb    1
78endstruc
79
80
81    ; Flags for DPT_ATA.bInitError
82    FLG_INITERROR_FAILED_TO_SELECT_DRIVE                EQU (1<<0)
83    FLG_INITERROR_FAILED_TO_INITIALIZE_CHS_PARAMETERS   EQU (1<<1)
84    FLG_INITERROR_FAILED_TO_SET_WRITE_CACHE             EQU (1<<2)
85    FLG_INITERROR_FAILED_TO_RECALIBRATE_DRIVE           EQU (1<<3)
86    FLG_INITERROR_FAILED_TO_SET_BLOCK_MODE              EQU (1<<4)
87    FLG_INITERROR_FAILED_TO_SET_PIO_MODE                EQU (1<<5)
88    FLG_INITERROR_FAILED_TO_INITIALIZE_STANDBY_TIMER    EQU (1<<6)
89
90; Additional variables needed to initialize and reset Advanced IDE Controllers.
91; EBDA must be reserved for DPTs when using these!
92%ifdef MODULE_ADVANCED_ATA
93struc DPT_ADVANCED_ATA
94    .dpt_ata                resb    DPT_ATA_size
95    .wControllerID          resb    2   ; Controller specific ID WORD (from Advanced Controller detection)
96    .wControllerBasePort    resb    2   ; Advanced Controller port (not IDE port)
97    .wMinPioCycleTime       resb    2   ; Minimum PIO Cycle Time in ns
98    .bPioMode               resb    1   ; Best supported PIO mode
99    .bDevice                resb    1   ; Device Type from IDEVARS (overrided when 32-bit controller detected)
100endstruc
101%endif
102
103
104; DPT for Serial devices
105%ifdef MODULE_SERIAL
106struc DPT_SERIAL
107    .dpt                    resb    DPT_size
108    .wSerialPortAndBaud:
109    .bSerialPort            resb    1   ; Serial connection I/O port address, divided by 4
110    .bSerialBaud            resb    1   ; Serial connection baud rate divisor
111endstruc
112%endif
113
114
115; This is the common size for all DPTs. All DPTs must be equal size.
116%ifdef MODULE_ADVANCED_ATA
117    LARGEST_DPT_SIZE            EQU     DPT_ADVANCED_ATA_size
118%else
119    LARGEST_DPT_SIZE            EQU     DPT_ATA_size
120%endif
121
122
123    ; Number of Sectors per Track is fixed to 63 for LBA assist calculation.
124    ; 1024 cylinders, 256 heads, 63 sectors = 8.4 GB limit (but DOS does not support more than 255 heads)
125    MAX_LCHS_CYLINDERS          EQU     1024
126    LBA_ASSIST_SPT              EQU     63
127
128
129;--------------------------------------------------------------------
130; LIMIT_LBA_CYLINDERS_IN_DXAX_TO_LCHS_CYLINDERS
131;   Parameters:
132;       DX:AX:  Number of LBA cylinders
133;   Returns:
134;       AX:     Number of L-CHS cylinders
135;   Corrupts registers:
136;       Nothing
137;--------------------------------------------------------------------
138%macro LIMIT_LBA_CYLINDERS_IN_DXAX_TO_LCHS_CYLINDERS 0
139    test    dx, dx
140    jnz     SHORT %%LoadMaxValueToAX
141    cmp     ax, MAX_LCHS_CYLINDERS
142    jb      SHORT %%NoNeedToModify
143%%LoadMaxValueToAX:
144    mov     ax, MAX_LCHS_CYLINDERS
145%%NoNeedToModify:
146%endmacro
147
148
149%endif ; CUSTOMDPT_INC
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