Changeset 370 in xtideuniversalbios for trunk/XTIDE_Universal_BIOS/Inc/IDE_8bit.inc

Timestamp:

Mar 29, 2012, 4:40:50 PM (12 years ago)

Author:

krille_n_@…

google:author:

krille_n_@hotmail.com

Message:

Changes:

• Added some missing PIO mode timings to ATA_ID.inc (based on info from ​http://www.singlix.net/specs/cfspc4_0.pdf)
• Updated Configuration_FullMode.txt but it may need additional changes as the Tandy info doesn't match the wiki.
• Optimizations.
• Excluded some unused code from XTIDECFG.

File:

• trunk/XTIDE_Universal_BIOS/Inc/IDE_8bit.inc (modified) (4 diffs)

trunk/XTIDE_Universal_BIOS/Inc/IDE_8bit.inc

@@ -30 +30 @@
 ; XTIDE_INSW
 ;   Parameters:
-;       BX:     Bit mask for toggling XTIDE data low/high reg
+;       BL:     Bit mask for toggling XTIDE data low/high reg
 ;       DX:     XTIDE Data Low Register address
 ;       ES:DI:  Ptr to destination buffer
@@ -41 +41 @@
 %ifdef USE_186  ; INS instruction available
     insb                        ; Load low byte from port DX to [ES:DI]
-    xor     dx, bx              ; IDE Data Reg to XTIDE Data High Reg
+    xor     dl, bl              ; IDE Data Reg to XTIDE Data High Reg
     insb                        ; Load high byte from port DX to [ES:DI]
-    xor     dx, bx              ; Restore to IDE Data Register
+    xor     dl, bl              ; Restore to IDE Data Register
 %else   ; If 8088/8086
     in      al, dx              ; Load low byte from port
-    xor     dx, bx              ; IDE Data Reg to XTIDE Data High Reg
+    xor     dl, bl              ; IDE Data Reg to XTIDE Data High Reg
     stosb                       ; Store byte to [ES:DI]
     in      al, dx              ; Load high byte from port
-    xor     dx, bx              ; Restore to IDE Data Register
+    xor     dl, bl              ; Restore to IDE Data Register
     stosb                       ; Store byte to [ES:DI]
 %endif
@@ -60 +60 @@
 ; XTIDE_OUTSW
 ;   Parameters:
-;       BX:     Bit mask for toggling XTIDE data low/high reg
+;       BL:     Bit mask for toggling XTIDE data low/high reg
 ;       DX:     XTIDE Data Low Register address
 ;       DS:SI:  Ptr to source buffer
@@ -71 +71 @@
 %ifdef USE_186  ; OUTS instruction available
     lodsb                       ; Load low byte from [DS:SI] to AL
-    xor     dx, bx              ; IDE Data Reg to XTIDE Data High Reg
+    xor     dl, bl              ; IDE Data Reg to XTIDE Data High Reg
     outsb                       ; Output high byte from [DS:SI]
-    xor     dx, bx              ; XTIDE Data High Reg to Data Low Reg
+    xor     dl, bl              ; XTIDE Data High Reg to Data Low Reg
     out     dx, al              ; Output low byte from AL
 %else   ; If 8088/8086
     lodsw                       ; Load word from [DS:SI]
-    xor     dx, bx              ; IDE Data Reg to XTIDE Data High Reg
+    xor     dl, bl              ; IDE Data Reg to XTIDE Data High Reg
     xchg    al, ah              ; => AL=high byte, AH=low byte
     out     dx, al              ; Output high byte
-    xor     dx, bx              ; XTIDE Data High Reg to Data Low Reg
+    xor     dl, bl              ; XTIDE Data High Reg to Data Low Reg
     mov     al, ah              ; Copy low byte to AL
     out     dx, al              ; Output low byte