Changeset 370 in xtideuniversalbios for trunk/XTIDE_Universal_BIOS/Inc


Ignore:
Timestamp:
Mar 29, 2012, 4:40:50 PM (12 years ago)
Author:
krille_n_@…
google:author:
krille_n_@hotmail.com
Message:

Changes:

  • Added some missing PIO mode timings to ATA_ID.inc (based on info from http://www.singlix.net/specs/cfspc4_0.pdf)
  • Updated Configuration_FullMode.txt but it may need additional changes as the Tandy info doesn't match the wiki.
  • Optimizations.
  • Excluded some unused code from XTIDECFG.
Location:
trunk/XTIDE_Universal_BIOS/Inc
Files:
3 edited

Legend:

Unmodified
Added
Removed
  • trunk/XTIDE_Universal_BIOS/Inc/ATA_ID.inc

    r364 r370  
    2121PIO_3_MIN_ADDRESS_VALID_NS  EQU     30
    2222PIO_4_MIN_ADDRESS_VALID_NS  EQU     25
    23 PIO_5_MIN_ADDRESS_VALID_NS  EQU     25      ; Could not find info
    24 PIO_6_MIN_ADDRESS_VALID_NS  EQU     25      ; Could not find info
     23PIO_5_MIN_ADDRESS_VALID_NS  EQU     15
     24PIO_6_MIN_ADDRESS_VALID_NS  EQU     10
    2525
    2626; PIO Minimum Active Times (t2)
     
    3030PIO_3_MIN_ACTIVE_TIME_NS    EQU     80
    3131PIO_4_MIN_ACTIVE_TIME_NS    EQU     70
    32 PIO_5_MIN_ACTIVE_TIME_NS    EQU     70      ; Could not find info
    33 PIO_6_MIN_ACTIVE_TIME_NS    EQU     70      ; Could not find info
     32PIO_5_MIN_ACTIVE_TIME_NS    EQU     65
     33PIO_6_MIN_ACTIVE_TIME_NS    EQU     55
    3434
    3535; PIO Minimum Recovery Times or Inactive Times (t2i) can be calculated
    36 ; from Minimum Cycle Time (t0) - Minimum Active Time (t2) - Address Valid Time (t1). 
     36; from Minimum Cycle Time (t0) - Minimum Active Time (t2) - Address Valid Time (t1).
    3737; I'm not sure about this calculation so correct me if I'm wrong!
    3838; Recovery time should be calculated at run time since Cycle Time t0 can be
     
    5454    .wBpTrck    resw 1  ; 4F, Number of unformatted bytes per track
    5555    .wBpSect    resw 1  ; 5F, Number of unformatted bytes per sector
    56     .wSPT       resw 1  ; 6F, Number of sectors per track 
     56    .wSPT       resw 1  ; 6F, Number of sectors per track
    5757                resw 3  ; 7...9X
    5858    .strSerial  resb 20 ; 10...19F, Serial number (20 ASCII characters, 0000h=not specified)
     
    136136                resw 1  ; 4X
    137137                resw 1  ; 5X
    138     .wSPT       resw 1  ; 6F, Number of logical sectors per track 
     138    .wSPT       resw 1  ; 6F, Number of logical sectors per track
    139139                resw 3  ; 7...9X
    140140    .strSerial  resb 20 ; 10...19F, Serial number (20 ASCII characters, 0000h=not specified)
     
    166166    .bBlockSel  resb 1  ; 59[0-7]V, Current setting for number of sectors that
    167167                        ;           can be transferred per interrupt on R/W multiple command
    168     .bBlockFlgs resb 1  ; 59[8-15]VR, bit 0 set if Multiple sector setting is valid 
     168    .bBlockFlgs resb 1  ; 59[8-15]VR, bit 0 set if Multiple sector setting is valid
    169169    .dwLBACnt   resd 1  ; 60...61F, Total number of user addressable sectors (LBA mode only)
    170170    .bSDMASupp  resb 1  ; 62[0-7]F, Single word DMA transfer modes supported
     
    172172    .bMDMASupp  resb 1  ; 63[0-7]F, Multiword DMA transfer modes supported
    173173    .bMDMAAct   resb 1  ; 63[8-15]V, Multiword DMA transfer mode active
    174    
     174
    175175    ; Words 64-70 are valid only if bit1 is set in .wFields (ATA2+)
    176176    .bPIOSupp   resb 1  ; 64[0-7]F, Advanced PIO Transfer Modes Supported
     
    220220                resw 1  ; 4X
    221221                resw 1  ; 5X
    222                 resw 1  ; 6X, Obsolete (Number of logical sectors per track) 
     222                resw 1  ; 6X, Obsolete (Number of logical sectors per track)
    223223                resw 2  ; 7...8V, Reserved for assignment by the CompactFlash Association
    224224                resw 1  ; 9X
  • trunk/XTIDE_Universal_BIOS/Inc/CustomDPT.inc

    r365 r370  
    9191struc DPT_SERIAL
    9292    .dpt                        resb    DPT_size
    93 
    9493    .wSerialPortAndBaud:
    9594    .bSerialPort                resb    1   ; Serial connection I/O port address, divided by 4
     
    126125    jnz     SHORT %%LoadMaxValueToAX
    127126    cmp     ax, MAX_LCHS_CYLINDERS
    128     jbe     SHORT %%NoNeedToModify
     127    jb      SHORT %%NoNeedToModify
    129128%%LoadMaxValueToAX:
    130129    mov     ax, MAX_LCHS_CYLINDERS
  • trunk/XTIDE_Universal_BIOS/Inc/IDE_8bit.inc

    r363 r370  
    3030; XTIDE_INSW
    3131;   Parameters:
    32 ;       BX:     Bit mask for toggling XTIDE data low/high reg
     32;       BL:     Bit mask for toggling XTIDE data low/high reg
    3333;       DX:     XTIDE Data Low Register address
    3434;       ES:DI:  Ptr to destination buffer
     
    4141%ifdef USE_186  ; INS instruction available
    4242    insb                        ; Load low byte from port DX to [ES:DI]
    43     xor     dx, bx              ; IDE Data Reg to XTIDE Data High Reg
     43    xor     dl, bl              ; IDE Data Reg to XTIDE Data High Reg
    4444    insb                        ; Load high byte from port DX to [ES:DI]
    45     xor     dx, bx              ; Restore to IDE Data Register
     45    xor     dl, bl              ; Restore to IDE Data Register
    4646%else   ; If 8088/8086
    4747    in      al, dx              ; Load low byte from port
    48     xor     dx, bx              ; IDE Data Reg to XTIDE Data High Reg
     48    xor     dl, bl              ; IDE Data Reg to XTIDE Data High Reg
    4949    stosb                       ; Store byte to [ES:DI]
    5050    in      al, dx              ; Load high byte from port
    51     xor     dx, bx              ; Restore to IDE Data Register
     51    xor     dl, bl              ; Restore to IDE Data Register
    5252    stosb                       ; Store byte to [ES:DI]
    5353%endif
     
    6060; XTIDE_OUTSW
    6161;   Parameters:
    62 ;       BX:     Bit mask for toggling XTIDE data low/high reg
     62;       BL:     Bit mask for toggling XTIDE data low/high reg
    6363;       DX:     XTIDE Data Low Register address
    6464;       DS:SI:  Ptr to source buffer
     
    7171%ifdef USE_186  ; OUTS instruction available
    7272    lodsb                       ; Load low byte from [DS:SI] to AL
    73     xor     dx, bx              ; IDE Data Reg to XTIDE Data High Reg
     73    xor     dl, bl              ; IDE Data Reg to XTIDE Data High Reg
    7474    outsb                       ; Output high byte from [DS:SI]
    75     xor     dx, bx              ; XTIDE Data High Reg to Data Low Reg
     75    xor     dl, bl              ; XTIDE Data High Reg to Data Low Reg
    7676    out     dx, al              ; Output low byte from AL
    7777%else   ; If 8088/8086
    7878    lodsw                       ; Load word from [DS:SI]
    79     xor     dx, bx              ; IDE Data Reg to XTIDE Data High Reg
     79    xor     dl, bl              ; IDE Data Reg to XTIDE Data High Reg
    8080    xchg    al, ah              ; => AL=high byte, AH=low byte
    8181    out     dx, al              ; Output high byte
    82     xor     dx, bx              ; XTIDE Data High Reg to Data Low Reg
     82    xor     dl, bl              ; XTIDE Data High Reg to Data Low Reg
    8383    mov     al, ah              ; Copy low byte to AL
    8484    out     dx, al              ; Output low byte
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