[587] | 1 | ; Project name : XTIDE Universal BIOS
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| 2 | ; Description : Functions for initializing Promise
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| 3 | ; PDC 20230 and 20630 VLB IDE Controllers.
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| 4 |
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| 5 | ;
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| 6 | ; XTIDE Universal BIOS and Associated Tools
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| 7 | ; Copyright (C) 2009-2010 by Tomi Tilli, 2011-2013 by XTIDE Universal BIOS Team.
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| 8 | ;
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| 9 | ; This program is free software; you can redistribute it and/or modify
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| 10 | ; it under the terms of the GNU General Public License as published by
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| 11 | ; the Free Software Foundation; either version 2 of the License, or
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| 12 | ; (at your option) any later version.
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| 13 | ;
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| 14 | ; This program is distributed in the hope that it will be useful,
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| 15 | ; but WITHOUT ANY WARRANTY; without even the implied warranty of
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| 16 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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| 17 | ; GNU General Public License for more details.
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| 18 | ; Visit http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
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| 19 | ;
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| 20 |
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| 21 | ; Section containing code
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| 22 | SECTION .text
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| 23 |
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| 24 | ;--------------------------------------------------------------------
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| 25 | ; PDC20x30_DetectControllerForIdeBaseInBX
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| 26 | ; Parameters:
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| 27 | ; BX: IDE Base Port
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| 28 | ; Returns:
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| 29 | ; AX: ID WORD for detected controller
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| 30 | ; DX: Controller base port
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| 31 | ; CF: Set if PDC detected
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| 32 | ; Corrupts registers:
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| 33 | ; BX (only when PDC detected)
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| 34 | ;--------------------------------------------------------------------
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| 35 | PDC20x30_DetectControllerForIdeBaseInBX:
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| 36 | mov dx, bx
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| 37 | call EnablePdcProgrammingMode
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[589] | 38 | jnz SHORT DisablePdcProgrammingMode.Return ; PDC controller not detected
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| 39 | ; ePUSH_T ax, DisablePdcProgrammingMode ; Uncomment this if GetPdcIDtoAX needs to be a real function
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| 40 | ; Fall to GetPdcIDtoAX
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| 41 |
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| 42 | ;--------------------------------------------------------------------
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| 43 | ; Programming mode must be enabled for this function.
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| 44 | ; This function also enables PDC 20630 extra registers.
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| 45 | ;
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| 46 | ; GetPdcIDtoAX
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| 47 | ; Parameters:
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| 48 | ; DX: IDE Base port
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| 49 | ; Returns:
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| 50 | ; AH: PDC ID
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| 51 | ; Corrupts registers:
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| 52 | ; AL, BX
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| 53 | ;--------------------------------------------------------------------
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| 54 | GetPdcIDtoAX:
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[622] | 55 | ;Force ID_PDC20230 instead of PDC20630 detection
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| 56 | ;mov ax, ID_PDC20230<<8
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| 57 | ;jmp SHORT DisablePdcProgrammingMode
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| 58 |
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[589] | 59 | push dx
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| 60 |
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| 61 | ; Try to enable PDC 20630 extra registers
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| 62 | add dx, BYTE LOW_CYLINDER_REGISTER
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| 63 | in al, dx
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| 64 | or al, FLG_PDCLCR_ENABLE_EXTRA_REGISTERS
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| 65 | out dx, al
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| 66 |
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| 67 | ; Try to access PDC 20630 registers to see if they are available
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| 68 | ; Hopefully this does not cause problems for systems with PDC 20230
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| 69 | add dx, BYTE PDC20630_INDEX_REGISTER - LOW_CYLINDER_REGISTER
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| 70 | mov al, PDCREG7_STATUS ; Try to access PDC 20630 status register
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| 71 | out dx, al
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| 72 | xchg bx, ax
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| 73 | in al, dx ; Does index register contain status register index?
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| 74 | cmp al, bl
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| 75 | mov ah, ID_PDC20630
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| 76 | eCMOVNE ah, ID_PDC20230
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| 77 |
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| 78 | pop dx
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| 79 | ; ret ; Uncomment this to make GetPdcIDtoAX a real function
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[587] | 80 | ; Fall to DisablePdcProgrammingMode
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| 81 |
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| 82 |
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| 83 | ;--------------------------------------------------------------------
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| 84 | ; DisablePdcProgrammingMode
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| 85 | ; Parameters:
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| 86 | ; DX: Base port
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| 87 | ; Returns:
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[589] | 88 | ; CF: Set
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[587] | 89 | ; Corrupts registers:
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| 90 | ; AL
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| 91 | ;--------------------------------------------------------------------
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| 92 | DisablePdcProgrammingMode:
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[622] | 93 | add dx, BYTE HIGH_CYLINDER_REGISTER ; 1F5h
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[587] | 94 | in al, dx
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[589] | 95 | add dx, -HIGH_CYLINDER_REGISTER ; Sets CF for PDC20x30_DetectControllerForIdeBaseInBX
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[622] | 96 | %if 0
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| 97 | ; Disassembly of VG4.BIN shows that bit 7 (programming mode activated)
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| 98 | ; is cleared manually after reading from HIGH_CYLINDER_REGISTER
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| 99 | ; That does not seem to be necessary.
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| 100 | inc dx
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| 101 | inc dx
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| 102 | call AdvAtaInit_InputWithDelay
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| 103 | and al, 7Fh
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| 104 | out dx, al
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| 105 | dec dx
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| 106 | dec dx
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| 107 | stc
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| 108 | %endif
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[589] | 109 | .Return:
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[587] | 110 | ret
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| 111 |
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| 112 |
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| 113 | ;--------------------------------------------------------------------
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| 114 | ; EnablePdcProgrammingMode
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| 115 | ; Parameters:
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| 116 | ; DX: Base port
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| 117 | ; Returns:
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[589] | 118 | ; CF: Cleared
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[587] | 119 | ; ZF: Set if programming mode enabled
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| 120 | ; Corrupts registers:
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| 121 | ; AL
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| 122 | ;--------------------------------------------------------------------
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| 123 | EnablePdcProgrammingMode:
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| 124 | ; Set bit 7 to sector count register
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[589] | 125 | inc dx
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| 126 | inc dx
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[622] | 127 | call AdvAtaInit_InputWithDelay ; 1F2h (SECTOR_COUNT_REGISTER)
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[587] | 128 | or al, 80h
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| 129 | out dx, al
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| 130 |
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[622] | 131 | ; PDC detection sequence
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| 132 | add dx, BYTE HIGH_CYLINDER_REGISTER - SECTOR_COUNT_REGISTER ; 5 - 2
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[587] | 133 | cli
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[622] | 134 | call AdvAtaInit_InputWithDelay ; 1F5
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| 135 |
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[587] | 136 | sub dx, BYTE HIGH_CYLINDER_REGISTER - SECTOR_COUNT_REGISTER
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[622] | 137 | call AdvAtaInit_InputWithDelay ; 1F2h
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| 138 |
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| 139 | add dx, STANDARD_CONTROL_BLOCK_OFFSET + (ALTERNATE_STATUS_REGISTER_in - SECTOR_COUNT_REGISTER) ; 200h+(6-2)
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| 140 | call AdvAtaInit_InputWithDelay ; 3F6h
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| 141 |
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| 142 | call AdvAtaInit_InputWithDelay ; 3F6h
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| 143 |
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[587] | 144 | sub dx, STANDARD_CONTROL_BLOCK_OFFSET + (ALTERNATE_STATUS_REGISTER_in - SECTOR_COUNT_REGISTER)
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[622] | 145 | call AdvAtaInit_InputWithDelay ; 1F2h
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| 146 |
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| 147 | call AdvAtaInit_InputWithDelay ; 1F2h
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[587] | 148 | sti
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| 149 |
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| 150 | ; PDC20230C and PDC20630 clears the bit we set at the beginning
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[622] | 151 | call AdvAtaInit_InputWithDelay ; 1F2h
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[589] | 152 | dec dx
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| 153 | dec dx ; Base port
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| 154 | test al, 80h ; Clears CF
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[587] | 155 | ret
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| 156 |
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| 157 |
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| 158 | ;--------------------------------------------------------------------
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| 159 | ; PDC20x30_GetMaxPioModeToALandMinPioCycleTimeToBX
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| 160 | ; Parameters:
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| 161 | ; AX: ID WORD specific for detected controller
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| 162 | ; Returns:
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[592] | 163 | ; AL: Max supported PIO mode (only if ZF set)
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| 164 | ; AH: ~FLGH_DPT_IORDY if IORDY not supported, -1 otherwise (only if ZF set)
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[587] | 165 | ; BX: Min PIO cycle time (only if ZF set)
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| 166 | ; ZF: Set if PIO limit necessary
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| 167 | ; Cleared if no need to limit timings
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| 168 | ; Corrupts registers:
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| 169 | ; Nothing
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| 170 | ;--------------------------------------------------------------------
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| 171 | PDC20x30_GetMaxPioModeToALandMinPioCycleTimeToBX:
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[592] | 172 | cmp ah, ID_PDC20230
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| 173 | jne SHORT .Return ; No need to limit anything for ID_PDC20630
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| 174 | mov ax, (~FLGH_DPT_IORDY & 0FFh) << 8 | 2 ; Limit PIO to 2 for ID_PDC20230
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[587] | 175 | mov bx, PIO_2_MIN_CYCLE_TIME_NS
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[589] | 176 | .Return:
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[587] | 177 | ret
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| 178 |
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| 179 |
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| 180 | ;--------------------------------------------------------------------
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| 181 | ; PDC20x30_InitializeForDPTinDSDI
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| 182 | ; Parameters:
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| 183 | ; DS:DI: Ptr to DPT for Single or Slave Drive
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| 184 | ; Returns:
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| 185 | ; AH: Int 13h return status
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| 186 | ; CF: Cleared if success or no controller to initialize
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| 187 | ; Set if error
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| 188 | ; Corrupts registers:
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| 189 | ; AL, BX, CX, DX
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| 190 | ;--------------------------------------------------------------------
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| 191 | PDC20x30_InitializeForDPTinDSDI:
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[589] | 192 | %ifdef USE_386
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| 193 | xor ch, ch
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| 194 | test BYTE [di+DPT.bFlagsLow], FLGL_DPT_SLAVE
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| 195 | setnz cl
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| 196 | %else
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[587] | 197 | xor cx, cx
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| 198 | test BYTE [di+DPT.bFlagsLow], FLGL_DPT_SLAVE
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[589] | 199 | jz SHORT .NotSlave
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| 200 | inc cx
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| 201 | .NotSlave:
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| 202 | %endif
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[587] | 203 |
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| 204 | mov dx, [di+DPT.wBasePort]
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| 205 | call EnablePdcProgrammingMode
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| 206 | call SetSpeedForDriveInCX
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| 207 | cmp BYTE [di+DPT_ADVANCED_ATA.wControllerID+1], ID_PDC20630
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[589] | 208 | jne SHORT .InitializationCompleted
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[587] | 209 | call SetPdc20630SpeedForDriveInCX
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[622] | 210 |
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| 211 | ; TODO: Should we first call SetPdc20630SpeedForDriveInCX and then
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| 212 | ; force SetSpeedForDriveInCX to PIO 0 (maximum speed setting 8)?
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| 213 | ; Need to test with PCD20630.
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| 214 |
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[589] | 215 | .InitializationCompleted:
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[587] | 216 | mov dx, [di+DPT.wBasePort]
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| 217 | call DisablePdcProgrammingMode
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| 218 | xor ah, ah
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| 219 | ret
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| 220 |
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| 221 |
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| 222 | ;--------------------------------------------------------------------
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| 223 | ; SetSpeedForDriveInCX
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| 224 | ; Parameters:
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| 225 | ; CX: 0 for master, 1 for slave drive
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| 226 | ; DX: IDE Base port
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| 227 | ; DS:DI: Ptr to DPT
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| 228 | ; Returns:
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[622] | 229 | ; DX: Sector Number Register (1F3h)
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[587] | 230 | ; Corrupts registers:
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| 231 | ; AX, BX
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| 232 | ;--------------------------------------------------------------------
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| 233 | SetSpeedForDriveInCX:
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[592] | 234 | mov bx, .rgbPioModeToPDCspeedValue
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| 235 | mov al, [di+DPT_ADVANCED_ATA.bPioMode]
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| 236 | MIN_U al, 2 ; Limit to PIO2
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| 237 | cs xlat
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| 238 | xchg bx, ax
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[587] | 239 |
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[622] | 240 | add dx, BYTE SECTOR_NUMBER_REGISTER ; 1F3h
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| 241 | mov bh, ~MASK_PDCSNR_DEV1SPEED ; Assume slave
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[588] | 242 | inc cx
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[622] | 243 | mov ah, 7 ; Max speed value. Set unknown bit 7 if either of drives are set to this
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[589] | 244 | loop .SetSpeed
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[622] | 245 | mov ah, 7 << POS_PDCSNR_DEV0SPEED
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| 246 | eSHL_IM bl, POS_PDCSNR_DEV0SPEED
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| 247 | mov bh, ~MASK_PDCSNR_DEV0SPEED
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[589] | 248 | .SetSpeed:
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[587] | 249 | in al, dx
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| 250 | and al, bh
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| 251 | or al, bl
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[622] | 252 | cmp bl, ah
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[589] | 253 | jb SHORT .OutputNewValue
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[622] | 254 | or al, FLG_PDCSNR_UNKNOWN_BIT7 ; Flag for PIO 2 and above?
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[589] | 255 | .OutputNewValue:
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| 256 | out dx, al
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[622] | 257 |
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| 258 | ; The above speed set does not work with Octek VL-COMBO rev 3.2 with PDC20230C
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| 259 | ; Only thing to make it work is to set FLG_PDCSCR_BOTHMAX to 1F2h. Are all PDC20230C controllers
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| 260 | ; like that? If so, why the above speed is not set? Or does the VL-COMBO or other PDC20230C
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| 261 | ; controllers have a jumper to prevent speed setup by software? (PDC20230B can only be set
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| 262 | ; by hardware, for example), like pin-compatible operation with older PDC20230B, perhaps?
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| 263 | ; Datasheets would be very useful...
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| 264 | ; For now, we just set the FLG_PDCSCR_BOTHMAX bit if either of the drives are set to speed 7
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| 265 | ;
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| 266 | ; Code below is not perfect. It does not properly test if both drives support PIO 2 but
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| 267 | ; likely if slave does, so does master (and if slave does not, we clear the
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| 268 | ; FLG_PDCSCR_BOTHMAX set by master)
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| 269 | mov bl, 1 ; Set bit 0, see VG4.BIN comments below
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| 270 | test al, al
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| 271 | jns SHORT .DoNotSetMaxSpeedBit
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| 272 | or bl, FLG_PDCSCR_BOTHMAX
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| 273 | .DoNotSetMaxSpeedBit:
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| 274 | dec dx ; SECTOR_COUNT_REGISTER, 1F2h
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| 275 | call AdvAtaInit_InputWithDelay
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| 276 | and al, ~FLG_PDCSCR_BOTHMAX
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| 277 | or al, bl
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| 278 | out dx, al
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| 279 |
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| 280 | ; VG4.BIN ("External BIOS") does the following after programming speed (1F3h)
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| 281 | ; (It never seems to set the speed bit we just set above).
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| 282 | ; The below code does not seem to have any effect, at least not for PDC20230C.
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| 283 | ; Why is bit 0 set to 1F2h?
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| 284 | ; Is it just to keep programming mode active if it has timeout, for example?
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| 285 | ; But after all that it just reads 1F5h to disable programming mode.
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| 286 | %if 0
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| 287 | ; Test code start
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| 288 | push cx
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| 289 | mov cx, 100
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| 290 | DELAY_WITH_LOOP_INSTRUCTION_NA
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| 291 |
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| 292 | ; Does below tell the controller that new speed is set?
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| 293 | in al, dx
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| 294 | or al, 1
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| 295 | out dx, al
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| 296 |
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| 297 | mov cx, 100
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| 298 | DELAY_WITH_LOOP_INSTRUCTION_NA
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| 299 | pop cx
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| 300 | ; Test code end
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| 301 | %endif
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| 302 |
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| 303 | inc dx ; SECTOR_NUMBER_REGISTER, 1F3h
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[589] | 304 | ret
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[587] | 305 |
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| 306 | .rgbPioModeToPDCspeedValue:
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| 307 | db 0 ; PIO 0
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| 308 | db 4 ; PIO 1
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| 309 | db 7 ; PIO 2
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| 310 |
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| 311 |
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| 312 | ;--------------------------------------------------------------------
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| 313 | ; SetPdc20630SpeedForDriveInCX
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| 314 | ; Parameters:
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| 315 | ; CX: 0 for master, 1 for slave drive
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| 316 | ; DS:DI: Ptr to DPT
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[622] | 317 | ; DX: Sector Number Register, 1F3h
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[587] | 318 | ; Returns:
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| 319 | ; DX: Low Cylinder Register
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| 320 | ; Corrupts registers:
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[589] | 321 | ; AX
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[587] | 322 | ;--------------------------------------------------------------------
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| 323 | SetPdc20630SpeedForDriveInCX:
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| 324 | inc dx ; LOW_CYLINDER_REGISTER
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[589] | 325 | mov ah, ~(FLG_PDCLCR_DEV0SPEED_BIT4 | FLG_PDCLCR_DEV0IORDY)
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| 326 | ror ah, cl
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[587] | 327 | in al, dx
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| 328 | and al, ah ; Clear drive specific bits
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| 329 | cmp BYTE [di+DPT_ADVANCED_ATA.bPioMode], 2
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[589] | 330 | jbe .ClearBitsOnly
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[587] | 331 | not ah
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| 332 | or al, ah
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[589] | 333 | .ClearBitsOnly:
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[587] | 334 | out dx, al
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| 335 | ret
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| 336 |
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