source: xtideuniversalbios/trunk/XTIDE_Universal_BIOS/Src/Initialization/AdvancedAta/AdvAtaInit.asm@ 624

Last change on this file since 624 was 623, checked in by Krister Nordvall, 2 years ago

Changes:

  • Reversed the change to IdeDPT.asm in r622 as it didn't work as intended.
  • Reordered some procedures to reduce alignment padding.
  • Added two new defines (EXTRA_LOOP_UNROLLING_SMALL and EXTRA_LOOP_UNROLLING_LARGE) that should improve transfer speeds for some hardware combinations, specifically 808x CPUs with any IDE controller using port I/O and any CPU with XT-IDE controllers.
  • Added a new define (USE_086) for use with 8086 and V30 CPUs only. Unlike the other USE_x86 defines, this define will not change the instruction set used and is therefore compatible with all CPUs. However, it will apply padding to make jump destinations WORD aligned which should improve performance on 8086/V30 CPUs but on 8088/V20 CPUs there is no benefit and, in addition to wasting ROM space, it might in fact be slower on these machines. Since the vast majority of XT class machines are using 8088/V20 CPUs this define is not used in the official XT builds - it's primarily intended for custom BIOS builds.
  • XTIDECFG: The URL to the support forum has been updated.
File size: 6.6 KB
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1; Project name : XTIDE Universal BIOS
2; Description : Common functions for initializing different
3; VLB and PCI IDE Controllers.
4
5;
6; XTIDE Universal BIOS and Associated Tools
7; Copyright (C) 2009-2010 by Tomi Tilli, 2011-2013 by XTIDE Universal BIOS Team.
8;
9; This program is free software; you can redistribute it and/or modify
10; it under the terms of the GNU General Public License as published by
11; the Free Software Foundation; either version 2 of the License, or
12; (at your option) any later version.
13;
14; This program is distributed in the hope that it will be useful,
15; but WITHOUT ANY WARRANTY; without even the implied warranty of
16; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17; GNU General Public License for more details.
18; Visit http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
19;
20
21; Section containing code
22SECTION .text
23
24;--------------------------------------------------------------------
25; AdvAtaInit_DetectControllerForIdeBaseInBX
26; Parameters:
27; BX: IDE Controller base port
28; Returns:
29; AX: ID WORD specific for detected controller
30; Zero if no controller detected
31; DX: Controller base port (not IDE)
32; CF: Set if controller detected
33; Cleared if no controller
34; Corrupts registers:
35; BX, CX
36;--------------------------------------------------------------------
37AdvAtaInit_DetectControllerForIdeBaseInBX:
38 ; Detect if system has PCI bus. If it does, we can skip VLB detection. This is a
39 ; good thing since detecting Vision QD6580 is dangerous since Intel PIIX4 south bridge
40 ; mirrors Interrupt Controller registers from Axh to Bxh. This can lead to faulty
41 ; detection of QD6580 that will eventually crash the system when ports are written.
42
43 ; We should save the 32-bit registers but we don't since system BIOS has stored
44 ; them already and we don't use the 32-bit registers ourselves anywhere at the moment.
45 push bx
46 push di
47; xor edi, edi ; Some BIOSes require this to be set to zero
48 ; *FIXME* The above instruction is commented away since RBIL says that this
49 ; only applies to software looking for the protected-mode entry point.
50 mov ax, PCI_INSTALLATION_CHECK ; May corrupt EAX, EBX, ECX, EDX, EDI
51 int BIOS_TIME_PCI_PNP_INTERRUPT_1Ah
52 pop di
53 pop bx
54 test ah, ah
55 jz SHORT .ThisSystemHasPCIbus
56
57 ; Detect VLB controllers
58 call Vision_DetectAndReturnIDinAXandPortInDXifControllerPresent
59 jnz SHORT .NoVisionControllerFound
60
61 call Vision_DoesIdePortInBXbelongToControllerWithIDinAX
62 jz SHORT .AdvancedControllerFoundForPortBX
63
64.NoVisionControllerFound:
65 call PDC20x30_DetectControllerForIdeBaseInBX
66 jnc SHORT .NoAdvancedControllerForPortBX
67
68.AdvancedControllerFoundForPortBX:
69 stc
70 ret
71
72.NoAdvancedControllerForPortBX:
73.ThisSystemHasPCIbus:
74 xor ax, ax ; Clear ID in AX and CF
75 ret
76
77
78;--------------------------------------------------------------------
79; AdvAtaInit_GetControllerMaxPioModeToALandMinPioCycleTimeToBX
80; Parameters:
81; AX: ID WORD specific for detected controller
82; Returns:
83; AL: Max supported PIO mode (only if ZF set)
84; AH: ~FLGH_DPT_IORDY if IORDY not supported, -1 otherwise (only if ZF set)
85; BX: Min PIO cycle time (only if ZF set)
86; ZF: Set if PIO limit necessary
87; Cleared if no need to limit timings
88; Corrupts registers:
89; Nothing
90;--------------------------------------------------------------------
91AdvAtaInit_GetControllerMaxPioModeToALandMinPioCycleTimeToBX:
92 cmp ah, ID_QD6580_ALTERNATE
93%ifdef USE_386
94 jae Vision_GetMaxPioModeToALandMinCycleTimeToBX
95 jmp PDC20x30_GetMaxPioModeToALandMinPioCycleTimeToBX
96%else
97 jae SHORT .Vision
98 jmp PDC20x30_GetMaxPioModeToALandMinPioCycleTimeToBX
99.Vision:
100 jmp Vision_GetMaxPioModeToALandMinCycleTimeToBX
101%endif
102
103
104;--------------------------------------------------------------------
105; AdvAtaInit_InitializeControllerForDPTinDSDI
106; Parameters:
107; DS:DI: Ptr to DPT for Single or Slave Drive
108; Returns:
109; AH: Int 13h return status
110; CF: Cleared if success or no controller to initialize
111; Set if error
112; Corrupts registers:
113; AL, BX, CX, DX
114;--------------------------------------------------------------------
115AdvAtaInit_InitializeControllerForDPTinDSDI:
116 ; Call Controller Specific initialization function
117 mov ax, [di+DPT_ADVANCED_ATA.wControllerID]
118 test ax, ax
119 jz SHORT .NoAdvancedController ; Return with CF cleared
120
121 cmp ah, ID_QD6580_ALTERNATE
122 jae SHORT .Vision
123 jmp PDC20x30_InitializeForDPTinDSDI
124
125.Vision:
126 push bp
127 push si
128
129 call AdvAtaInit_LoadMasterDPTtoDSSIifSlaveInDSDI
130 call Vision_InitializeWithIDinAH
131 xor ax, ax ; Success
132
133 pop si
134 pop bp
135
136.NoAdvancedController:
137 ret
138
139
140;--------------------------------------------------------------------
141; AdvAtaInit_LoadMasterDPTtoDSSIifSlaveInDSDI
142; Parameters:
143; DS:DI: Ptr to DPT for Single or Slave Drive
144; Returns:
145; SI: Offset to Master DPT if Slave Drive present
146; Zero if Slave Drive not present
147; Corrupts registers:
148; AL
149;--------------------------------------------------------------------
150AdvAtaInit_LoadMasterDPTtoDSSIifSlaveInDSDI:
151 ; Must be Slave Drive if previous DPT has same IDEVARS offset
152 lea si, [di-LARGEST_DPT_SIZE] ; DS:SI points to previous DPT
153 mov al, [di+DPT.bIdevarsOffset]
154 cmp al, [si+DPT.bIdevarsOffset]
155 je SHORT .MasterAndSlaveDrivePresent
156
157 ; We only have single drive so zero SI
158 xor si, si
159.MasterAndSlaveDrivePresent:
160 ret
161
162
163;--------------------------------------------------------------------
164; AdvAtaInit_SelectSlowestCommonPioTimingsToBXandCXfromDSSIandDSDI
165; Parameters:
166; DS:DI: Ptr to DPT for Single or Slave Drive
167; SI: Offset to Master DPT if Slave Drive present
168; Zero if Slave Drive not present
169; Returns:
170; BX: Best common PIO mode
171; CX: Slowest common PIO Cycle Time in nanosecs
172; Corrupts registers:
173; Nothing
174;--------------------------------------------------------------------
175AdvAtaInit_SelectSlowestCommonPioTimingsToBXandCXfromDSSIandDSDI:
176 eMOVZX bx, [di+DPT_ADVANCED_ATA.bPioMode]
177 mov cx, [di+DPT_ADVANCED_ATA.wMinPioCycleTime]
178 test si, si
179 jz SHORT .PioTimingsLoadedToBXandCX
180 MIN_U bl, [si+DPT_ADVANCED_ATA.bPioMode]
181 MAX_U cx, [si+DPT_ADVANCED_ATA.wMinPioCycleTime]
182.PioTimingsLoadedToBXandCX:
183 ret
184
185
186;--------------------------------------------------------------------
187; Just a simple IN AL, DX instruction but the function call works
188; as I/O delay.
189;
190; AdvAtaInit_InputWithDelay
191; Parameters:
192; DX: Port to read from
193; Returns:
194; AL: Byte read from port
195; Corrupts registers:
196; Nothing
197;--------------------------------------------------------------------
198AdvAtaInit_InputWithDelay:
199 in al, dx
200 ret
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