source: xtideuniversalbios/trunk/XTIDE_Universal_BIOS/Src/Device/IDE/IdeIO.asm@ 167

Last change on this file since 167 was 160, checked in by Tomi Tilli, 14 years ago

Changes to XTIDE Universal BIOS:

  • Support for XTIDE mod now works.
File size: 2.7 KB
RevLine 
[150]1; Project name : XTIDE Universal BIOS
2; Description : IDE Register I/O functions.
3
4; Section containing code
5SECTION .text
6
7;--------------------------------------------------------------------
[160]8; IdeIO_OutputALtoIdeRegisterInDL
[150]9; Parameters:
10; AL: Byte to output
[160]11; DL: IDE Register
12; DS:DI: Ptr to DPT (in RAMVARS segment)
[150]13; Returns:
14; Nothing
15; Corrupts registers:
[160]16; BX, DX
[150]17;--------------------------------------------------------------------
18ALIGN JUMP_ALIGN
[160]19IdeIO_OutputALtoIdeRegisterInDL:
20 mov bx, IDEVARS.wPort
21 call GetPortToDXandTranslateA0andA3ifNecessary
[150]22 out dx, al
23 ret
24
25
26;--------------------------------------------------------------------
[160]27; IdeIO_OutputALtoIdeControlBlockRegisterInDL
[150]28; Parameters:
29; AL: Byte to output
[160]30; DL: IDE Control Block Register
31; DS:DI: Ptr to DPT (in RAMVARS segment)
[150]32; Returns:
33; Nothing
34; Corrupts registers:
[160]35; BX, DX
[150]36;--------------------------------------------------------------------
37ALIGN JUMP_ALIGN
[160]38IdeIO_OutputALtoIdeControlBlockRegisterInDL:
39 mov bx, IDEVARS.wPortCtrl
40 call GetPortToDXandTranslateA0andA3ifNecessary
[150]41 out dx, al
42 ret
43
44
45;--------------------------------------------------------------------
[160]46; IdeIO_InputToALfromIdeRegisterInDL
[150]47; Parameters:
[160]48; DL: IDE Register
49; DS:DI: Ptr to DPT (in RAMVARS segment)
[150]50; Returns:
51; AL: Inputted byte
52; Corrupts registers:
[160]53; BX, DX
[150]54;--------------------------------------------------------------------
55ALIGN JUMP_ALIGN
[160]56IdeIO_InputToALfromIdeRegisterInDL:
57 mov bx, IDEVARS.wPort
58 call GetPortToDXandTranslateA0andA3ifNecessary
[150]59 in al, dx
60 ret
[160]61
62
63;--------------------------------------------------------------------
64; GetPortToDXandTranslateA0andA3ifNecessary
65; Parameters:
66; BX: Offset to port in IDEVARS (IDEVARS.wPort or IDEVARS.wPortCtrl)
67; DL: IDE Register
68; DS:DI: Ptr to DPT (in RAMVARS segment)
69; Returns:
70; DX: Source/Destination Port
71; Corrupts registers:
72; BX
73;--------------------------------------------------------------------
74ALIGN JUMP_ALIGN
75GetPortToDXandTranslateA0andA3ifNecessary:
76 xor dh, dh ; DX now has IDE register offset
77 add bl, [di+DPT.bIdevarsOffset] ; CS:BX now points port address
78 add dx, [cs:bx]
79 test BYTE [di+DPT.bFlagsHigh], FLGH_DPT_REVERSED_A0_AND_A3
80 jz SHORT .ReturnPortInDX
81
82 ; Exchange address lines A0 and A3 from DL
83 mov bl, dl
84 mov bh, MASK_A3_AND_A0_ADDRESS_LINES
85 and bh, bl ; BH = 0, 1, 8 or 9, we can ignore 0 and 9
86 jz SHORT .ReturnPortInDX ; Jump out since DH is 0
87 xor bh, MASK_A3_AND_A0_ADDRESS_LINES
88 jz SHORT .ReturnPortInDX ; Jump out since DH was 9
89 and dl, ~MASK_A3_AND_A0_ADDRESS_LINES
90 or dl, bh ; Address lines now reversed
91.ReturnPortInDX:
92 ret
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