source: xtideuniversalbios/trunk/XTIDE_Universal_BIOS/Inc/CustomDPT.inc@ 162

Last change on this file since 162 was 158, checked in by Tomi Tilli, 14 years ago

Changes to XTIDE Universal BIOS:

  • Optimized few bytes.
File size: 2.6 KB
Line 
1; Project name : XTIDE Universal BIOS
2; Description : Defines for DPT structs containing custom
3; Disk Parameter Table used by this BIOS.
4%ifndef CUSTOMDPT_INC
5%define CUSTOMDPT_INC
6
7; Base DPT for all device types
8struc DPT ; 8 bytes
9 ; General Disk Parameter Table related
10 .wFlags:
11 .bFlagsLow resb 1
12 .bFlagsHigh resb 1
13 .bIdevarsOffset resb 1 ; Offset to IDEVARS for this drive
14
15 ; L-CHS to P-CHS and L-CHS to LBA28 conversion related
16 .bLchsHeads resb 1 ; Number of L-CHS Heads (1...255)
17
18 ; IDE Drive related
19 .wPchsCylinders resb 2 ; Number of P-CHS (IDE) Cylinders (1...16383)
20 .wPchsHeadsAndSectors:
21 .bPchsHeads resb 1 ; Number of P-CHS (IDE) Heads (1...16)
22 .bPchsSectors resb 1 ; Number of P-CHS (IDE) Sectors per Track (1...63)
23endstruc
24
25; DPT for ATA devices
26struc DPT_ATA ; 8 + 2 bytes = 10 bytes
27 .dpt resb DPT_size
28
29 ; Block size is specified in sectors (1, 2, 4, 8, 16, 32 or 64).
30 ; 128 is not allowed to prevent offset overflow during data transfer.
31 .wSetAndMaxBlock:
32 .bSetBlock resb 1 ; Current block size (at least 1)
33 .bMaxBlock resb 1 ; Maximum block size, 0 = block mode not supported
34endstruc
35
36LARGEST_DPT_SIZE EQU DPT_ATA_size
37
38
39; Bit definitions for DPT.bFlagsLow
40MASKL_DPT_CHS_SHIFT_COUNT EQU (7<<0) ; Bits 0...3, P-CHS to L-CHS bit shift count (0...4)
41FLGL_DPT_SLAVE EQU FLG_DRVNHEAD_DRV ; (1<<4), Drive is slave drive
42MASKL_DPT_ADDRESSING_MODE EQU (3<<5) ; Bits 5..6, Addressing Mode (bit 6 == FLG_DRVNHEAD_LBA)
43FLGL_DPT_ENABLE_IRQ EQU (1<<7)
44
45; Bit definitions for DPT.bFlagsHigh
46FLGH_DPT_REVERSED_A0_AND_A3 EQU (1<<0) ; XTIDE mod, Address lines 0 and 3 reversed
47FLGH_DPT_SERIAL_DEVICE EQU (1<<1) ; Serial Port Device
48FLGH_DPT_BLOCK_MODE_SUPPORTED EQU (1<<2) ; Use block transfer commands
49FLGH_DPT_INTERRUPT_IN_SERVICE EQU (1<<3) ; Set when waiting for IRQ
50FLGH_DPT_RESET_nDRDY EQU (1<<4) ; Drive ready to accept commands
51FLGH_DPT_RESET_nINITPRMS EQU (1<<5) ; Initialize Device Parameters successfull
52FLGH_DPT_RESET_nRECALIBRATE EQU (1<<6) ; Recalibrate successfull
53FLGH_DPT_RESET_nSETBLOCK EQU (1<<7) ; Initialize Block Mode successfull
54MASKH_DPT_RESET EQU 0F0h
55
56; Addressing modes for DPT.wFlags
57ADDRESSING_MODE_FIELD_POSITION EQU 5
58ADDRESSING_MODE_LCHS EQU 0 ; L-CHS Addressing Mode (NORMAL in many other BIOSes)
59ADDRESSING_MODE_PCHS EQU 1 ; P-CHS Addressing Mode (LARGE in many other BIOSes)
60ADDRESSING_MODE_LBA28 EQU 2 ; 28-bit LBA Addressing Mode
61ADDRESSING_MODE_LBA48 EQU 3 ; 48-bit LBA Addressing Mode
62
63
64%endif ; CUSTOMDPT_INC
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