source: xtideuniversalbios/trunk/XTIDE_Universal_BIOS/Inc/CustomDPT.inc@ 538

Last change on this file since 538 was 536, checked in by krille_n_@…, 11 years ago

Changes:

  • Added support for the Silicon Valley Computer ADP50L controller (and possibly other IDE controllers from SVC using memory mapped I/O). Please note that this has not been tested in any way since I don't have any of these cards myself (make backups before trying this on drives with important data). Also, *if* it works, make sure it works reliably (stress test the disk system). Some things you should know: 1) Autodetection for this controller has not been added to XTIDECFG, you need to manually select the "SVC ADP50L" controller (and possibly change the BIOS segment address if not using the default of C800h). 2) The memory mapped I/O window is inside the ROM address space of the controller. The XTIDE Universal BIOS currently do not support this so that means you need to use another ROM (for example, an XTIDE or XTCF card or the BOOT ROM of a NIC). This presents another problem, the original ADP50L BIOS needs to be disabled somehow to avoid conflicts. Either pull the ROM chip or disable the BIOS by removing jumper J3. Note, I have no idea if any of this will actually work. It's basically a shot in the dark.
File size: 5.6 KB
RevLine 
[99]1; Project name : XTIDE Universal BIOS
[3]2; Description : Defines for DPT structs containing custom
3; Disk Parameter Table used by this BIOS.
[376]4
5;
[399]6; XTIDE Universal BIOS and Associated Tools
[526]7; Copyright (C) 2009-2010 by Tomi Tilli, 2011-2013 by XTIDE Universal BIOS Team.
[376]8;
9; This program is free software; you can redistribute it and/or modify
10; it under the terms of the GNU General Public License as published by
11; the Free Software Foundation; either version 2 of the License, or
12; (at your option) any later version.
[399]13;
[376]14; This program is distributed in the hope that it will be useful,
15; but WITHOUT ANY WARRANTY; without even the implied warranty of
16; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
[399]17; GNU General Public License for more details.
[376]18; Visit http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
19;
20
[3]21%ifndef CUSTOMDPT_INC
22%define CUSTOMDPT_INC
23
[150]24; Base DPT for all device types
[472]25struc DPT
[473]26 ; General Disk Parameter Table related
[158]27 .wFlags:
[399]28 .bFlagsLow resb 1
29 .bFlagsHigh resb 1
30 .bIdevarsOffset resb 1 ; Offset to IDEVARS for this drive
[422]31 .bInitError resb 1 ; Flags for AH=09h initialization errors
[536]32 .wBasePort resb 2 ; Segment for JR-IDE/ISA and ADP50L
[3]33
[473]34 ; CHS variables
[421]35 .wLchsCylinders resb 2 ; (1...1027, yes 1027)
36 .wLchsHeadsAndSectors:
37 .bLchsHeads resb 1 ; (1...255)
38 .bLchsSectorsPerTrack resb 1 ; (1...63)
[422]39 .bPchsHeads resb 1 ; (1...16)
[238]40
[422]41 ; LBA and remaining P-CHS variables
[421]42%ifdef MODULE_EBIOS
[422]43 .bPchsSectorsPerTrack resb 1
44 .wPchsCylinders resb 2
[421]45 .twLbaSectors resb 6 ; 48-bit sector count for LBA addressing
46%endif
[491]47 alignb 2 ; WORD alignment for DPT_SERIAL or DPT_ATA
[150]48endstruc
[3]49
[399]50 ; Bit definitions for DPT.bFlagsLow
[421]51 MASKL_DPT_CHS_SHIFT_COUNT EQU (3<<0) ; Bits 0...1, P-CHS to L-CHS bit shift count (0...3)
[422]52 MASKL_DPT_TRANSLATEMODE EQU MASK_DRVPARAMS_TRANSLATEMODE ; Bits 2...3, NORMAL, LARGE or Assisted LBA addressing mode
53 FLGL_DPT_ASSISTED_LBA EQU (1<<(TRANSLATEMODE_FIELD_POSITION+1))
[421]54 FLGL_DPT_SLAVE EQU FLG_DRVNHEAD_DRV ; Bit 4, Drive is a Slave Drive
[411]55%ifdef MODULE_IRQ
[421]56 FLGL_DPT_ENABLE_IRQ EQU (1<<5) ; Bit 5, Enable IRQ
[411]57%endif
[421]58%ifdef MODULE_EBIOS
59 FLGL_DPT_LBA_AND_EBIOS_SUPPORTED EQU FLG_DRVNHEAD_LBA ; Bit 6, Drive supports LBA and so EBIOS functions can be supported
60 FLGL_DPT_LBA48 EQU (1<<7) ; Bit 7, Drive supports 48-bit LBA (Must be bit 7!)
61%endif
[3]62
[421]63
[399]64 ; Bit definitions for DPT.bFlagsHigh
[421]65 FLGH_DPT_BLOCK_MODE_SUPPORTED EQU (1<<1) ; Bit 1, Use block transfer commands (must be bit 1!)
[411]66%ifdef MODULE_SERIAL
[421]67 FLGH_DPT_SERIAL_DEVICE EQU (1<<2) ; Bit 2, Serial Port Device
[411]68%endif
69%ifdef MODULE_IRQ
[421]70 FLGH_DPT_INTERRUPT_IN_SERVICE EQU (1<<3) ; Bit 3, Set when waiting for IRQ
[411]71%endif
72%ifdef MODULE_FEATURE_SETS
[505]73 FLGH_DPT_POWER_MANAGEMENT_SUPPORTED EQU (1<<5) ; Bit 5, Drive supports power management
[411]74%endif
75%ifdef MODULE_ADVANCED_ATA
[505]76 FLGH_DPT_IORDY EQU (1<<7) ; Bit 7, Controller and Drive supports IORDY
[411]77%endif
[363]78
[399]79 ; Serial device only
[411]80%ifdef MODULE_SERIAL_FLOPPY
[399]81 FLGH_DPT_SERIAL_FLOPPY EQU (1<<4)
82 FLGH_DPT_SERIAL_FLOPPY_TYPE_MASK EQU 0e0h
83 FLGH_DPT_SERIAL_FLOPPY_TYPE_FIELD_POSITION EQU 5
[411]84%endif
[258]85
[3]86
[422]87 ; Flags for DPT_ADVANCED_ATA.bInitError
88 FLG_INITERROR_FAILED_TO_SELECT_DRIVE EQU (1<<0)
89 FLG_INITERROR_FAILED_TO_INITIALIZE_CHS_PARAMETERS EQU (1<<1)
90 FLG_INITERROR_FAILED_TO_SET_WRITE_CACHE EQU (1<<2)
91 FLG_INITERROR_FAILED_TO_RECALIBRATE_DRIVE EQU (1<<3)
92 FLG_INITERROR_FAILED_TO_SET_BLOCK_MODE EQU (1<<4)
93 FLG_INITERROR_FAILED_TO_SET_PIO_MODE EQU (1<<5)
94 FLG_INITERROR_FAILED_TO_INITIALIZE_STANDBY_TIMER EQU (1<<6)
[473]95 FLG_INITERROR_FAILED_TO_SET_XTCF_MODE EQU (1<<7)
[480]96 FLG_INITERROR_FAILED_TO_SET_8BIT_MODE EQU FLG_INITERROR_FAILED_TO_SET_XTCF_MODE
[363]97
[422]98
99
[363]100; DPT for ATA devices
[473]101struc DPT_ATA
[399]102 .dpt resb DPT_size
[473]103 .bDevice resb 1 ; Device Type from IDEVARS (overrided when 32-bit controller detected)
[399]104 .bBlockSize resb 1 ; Current block size in sectors (do not set to zero!)
[363]105endstruc
106
107
[421]108
[364]109; Additional variables needed to initialize and reset Advanced IDE Controllers.
110; EBDA must be reserved for DPTs when using these!
[363]111%ifdef MODULE_ADVANCED_ATA
[473]112struc DPT_ADVANCED_ATA
[363]113 .dpt_ata resb DPT_ATA_size
[364]114 .wControllerID resb 2 ; Controller specific ID WORD (from Advanced Controller detection)
[363]115 .wControllerBasePort resb 2 ; Advanced Controller port (not IDE port)
[364]116 .wMinPioCycleTime resb 2 ; Minimum PIO Cycle Time in ns
117 .bPioMode resb 1 ; Best supported PIO mode
[472]118 alignb 2
[363]119endstruc
[411]120%endif
[363]121
[400]122
[364]123; DPT for Serial devices
[363]124%ifdef MODULE_SERIAL
[473]125struc DPT_SERIAL
[399]126 .dpt resb DPT_size
[363]127 .wSerialPortAndBaud:
[399]128 .bSerialPort resb 1 ; Serial connection I/O port address, divided by 4
129 .bSerialBaud resb 1 ; Serial connection baud rate divisor
[363]130endstruc
[474]131
132; On performance critical situations we compare DPT_ATA.bDevice without checking FLGH_DPT_SERIAL_DEVICE
133; first! DPT_ATA.bDevice uses small values so there will be no problems.
[488]134%ifndef CHECK_FOR_UNUSED_ENTRYPOINTS
[491]135 %if DPT_SERIAL.bSerialPort <> DPT_ATA.bDevice
136 %error "DPT_ATA.bDevice and DPT_SERIAL.bSerialPort must be in same offsets!"
137 %endif
[363]138%endif
[491]139%endif ; MODULE_SERIAL
[363]140
141
142; This is the common size for all DPTs. All DPTs must be equal size.
[364]143%ifdef MODULE_ADVANCED_ATA
[399]144 LARGEST_DPT_SIZE EQU DPT_ADVANCED_ATA_size
[364]145%else
[399]146 LARGEST_DPT_SIZE EQU DPT_ATA_size
[364]147%endif
[363]148
149
[399]150 ; Number of Sectors per Track is fixed to 63 for LBA assist calculation.
151 ; 1024 cylinders, 256 heads, 63 sectors = 8.4 GB limit (but DOS does not support more than 255 heads)
152 MAX_LCHS_CYLINDERS EQU 1024
153 LBA_ASSIST_SPT EQU 63
[3]154
[173]155
[3]156%endif ; CUSTOMDPT_INC
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