| 1 | ; Project name : XTIDE Universal BIOS
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| 2 | ; Description : Promise PDC 20230-C and 20630 VLB IDE controller
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| 3 | ; specifications.
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| 4 |
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| 5 | ;
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| 6 | ; XTIDE Universal BIOS and Associated Tools
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| 7 | ; Copyright (C) 2009-2010 by Tomi Tilli, 2011-2013 by XTIDE Universal BIOS Team.
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| 8 | ;
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| 9 | ; This program is free software; you can redistribute it and/or modify
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| 10 | ; it under the terms of the GNU General Public License as published by
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| 11 | ; the Free Software Foundation; either version 2 of the License, or
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| 12 | ; (at your option) any later version.
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| 13 | ;
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| 14 | ; This program is distributed in the hope that it will be useful,
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| 15 | ; but WITHOUT ANY WARRANTY; without even the implied warranty of
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| 16 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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| 17 | ; GNU General Public License for more details.
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| 18 | ; Visit http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
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| 19 | ;
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| 20 |
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| 21 | %ifndef PDC20x30_INC
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| 22 | %define PDC20x30_INC
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| 23 |
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| 24 | ;
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| 25 |
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| 26 | ; SECTOR_COUNT_REGISTER (1F2) in programming mode
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| 27 | FLG_PDCSCR_BOTHMAX EQU (1<<6) ; Master and Slave at maximum speed
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| 28 |
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| 29 | ; SECTOR_NUMBER_REGISTER (1F3) in programming mode
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| 30 | FLG_PDCSNR_UNKNOWN_BIT7 EQU (1<<7) ; Set to 1 for speed setting 7 of device 0 or 1
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| 31 | FLG_PDCSNR_ID3 EQU (1<<6) ; VLB bus speed: 0 > 33 MHz, 1 <= 33 MHz
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| 32 | POS_PDCSNR_DEV0SPEED EQU 3
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| 33 | MASK_PDCSNR_DEV0SPEED EQU (7<<POS_PDCSNR_DEV0SPEED) ; 0 to 7
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| 34 | MASK_PDCSNR_DEV1SPEED EQU (7<<0) ; 0 to 7
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| 35 |
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| 36 | ; Disassembly of VG4.BIN: (might have errors)
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| 37 | ; FLG_PDCSNR_UNKNOWN_BIT7 will be set if no dev1, no matter what speed
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| 38 | ; FLG_PDCSNR_UNKNOWN_BIT7 will be cleared if dev1 found but no master
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| 39 | ; FLG_PDCSNR_UNKNOWN_BIT7 will be cleared if dev0 and dev1 speeds are both 7 !
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| 40 | ; FLG_PDCSNR_UNKNOWN_BIT7 will be cleared if dev 1 is 7 !
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| 41 | ; If dev 1 is 6 or less and dev 0 is 7, then dev0-- and set FLG_PDCSCR_UNKNOWN_BIT7
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| 42 | ;
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| 43 |
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| 44 |
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| 45 |
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| 46 | ; LOW_CYLINDER_REGISTER in programming mode
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| 47 | ; This is only on PDC 20630!
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| 48 | FLG_PDCLCR_DEV0SPEED_BIT4 EQU (1<<7) ; Possibly speed bit 4 (speed settings 8 to 15)?
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| 49 | FLG_PDCLCR_DEV1SPEED_BIT4 EQU (1<<6) ; Same as above but for device 1
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| 50 | FLG_PDCLCR_DEV0IORDY EQU (1<<5) ; Not sure about this
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| 51 | FLG_PDCLCR_DEV1IORDY EQU (1<<4) ; Same as above but for device 1
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| 52 | FLG_PDCLCR_ENABLE_EXTRA_REGISTERS EQU (1<<3)
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| 53 |
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| 54 |
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| 55 | ; PDC 20630 specific registers mapped after IDE registers
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| 56 | PDC20630_INDEX_REGISTER EQU 8 ; 1F8h
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| 57 | PDC20630_DATA_REGISTER EQU 9 ; 1F9h
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| 58 |
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| 59 | ; PDC 20630 registers to access through index and data register
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| 60 | PDCREG0_TIMING_OF_DEV0_LOW EQU 0 ; Low, high, what timings?
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| 61 | PDCREG1_TIMING_OF_DEV0_HIGH EQU 1
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| 62 | PDCREG2_TIMING_OF_DEV1_LOW EQU 2
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| 63 | PDCREG3_TIMING_OF_DEV1_HIGH EQU 3
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| 64 | PDCREG7_STATUS EQU 7
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| 65 |
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| 66 | FLG_PDCSTATUS_DMA_ERROR EQU (1<<4) ; ?
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| 67 | FLG_PDCSTATUS_DMA_READ_COMPLETED EQU (1<<1) ; ?
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| 68 | FLG_PDCSTATUS_DMA_WRITE_COMPLETED EQU (1<<0) ; ?
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| 69 |
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| 70 |
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| 71 | %endif ; PDC20x30_INC
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