Changeset 558 in xtideuniversalbios for trunk/XTIDE_Universal_BIOS/Inc


Ignore:
Timestamp:
Jun 23, 2013, 3:52:31 PM (11 years ago)
Author:
krille_n_@…
google:author:
krille_n_@hotmail.com
Message:

Changes:

  • Building the BIOS Drive Information Tool now works again.
  • Moved all XT-CF related code to MODULE_8BIT_IDE_ADVANCED. I don't see how an XT-CF card could work without *_ADVANCED anyway but if I'm wrong, feel free to undo this. Note! The autodetection code in XTIDECFG has NOT been changed to reflect this (still relies on MODULE_8BIT_IDE).
  • Optimizations and fixes in general.
Location:
trunk/XTIDE_Universal_BIOS/Inc
Files:
3 edited

Legend:

Unmodified
Added
Removed

  • trunk/XTIDE_Universal_BIOS/Inc/Controllers/Vision.inc

    r540 r558  
    2828QD65XX_BASE_PORT                    EQU     30h
    2929QD65XX_ALTERNATIVE_BASE_PORT        EQU     0B0h    ; This is the default setting but Intel PIIX4 South Bridge
    30                                                     ; (and likely other PCI chisets as well) mirror PIC registers here
     30                                                    ; (and likely other PCI chipsets as well) mirror PIC registers here
    3131
    3232; Vision Register offsets from QD chip base port

  • trunk/XTIDE_Universal_BIOS/Inc/Controllers/XTCF.inc

    r545 r558  
    2626%define XTCF_INC
    2727
    28 ; XT-CF requires that block must be less than 128 sectors (64 kiB) for DMA
    29 ; transfers.
    30 ;
     28; XT-CF requires that block must be less than 128 sectors (64 kiB) for DMA transfers.
     29;
    3130; Note: XT-CFv3 DMA will not interfere with PC & PC/XT memory refresh,
    3231; since the XT-CFv3 detaches itself from the bus every 16 bytes transferred.
    … …  
    5958; XT-CFv3 cannot be distinguised by software, so user must decide and set
    6059; the mode via a call to Int 13h function 1Eh accordingly (see AH1E_XTCF.asm).
    61 ;;
     60;
    6261XTCF_8BIT_PIO_MODE                  EQU     00h
    6362XTCF_8BIT_PIO_MODE_WITH_BIU_OFFLOAD EQU     01h
    … …  
    8079; SET_XTCF_TRANSFER_MODE
    8180;   Parameters:
    82 ;       DH:     Mode to select,
    83 ;                               i.e. XTCF_8BIT_PIO_MODE
    84 ;               Note there's no way to know if an
    85 ;               XT-CF adapter supports DMA, so the
    86 ;               user should enable DMA only if a
    87 ;               DMA-enabled XT-CFv3 is fitted.
     81;       DH:     Mode to select, i.e. XTCF_8BIT_PIO_MODE
     82;               Note there's no way to know if an XT-CF adapter
     83;               supports DMA, so the user should enable DMA
     84;               only if a DMA-enabled XT-CFv3 is fitted.
    8885;       DL:     Drive Number
    8986;--------------------------------------------------------------------
    … …  
    9592;       DL:     Drive Number
    9693;   Returns:
    97 ;       DL:     Block mode sectors per block
    98 ;               configured
    9994;       DH:     One of the mode values listed above,
    100 ;                               i.e. XTCF_8BIT_PIO_MODE
     95;               i.e. XTCF_8BIT_PIO_MODE
     96;       DL:     Block mode sectors per block configured
    10197;--------------------------------------------------------------------
    10298GET_XTCF_TRANSFER_MODE              EQU     2

  • trunk/XTIDE_Universal_BIOS/Inc/RomVars.inc

    r547 r558  
    121121STANDARD_CONTROL_BLOCK_OFFSET           EQU     200h
    122122XTIDE_CONTROL_BLOCK_OFFSET              EQU     8h      ; for XTIDE, A3 is used to control selected register (CS0 vs CS1)...
    123 XTCF_CONTROL_BLOCK_OFFSET               EQU     10h     ; ...and for XT-CF (all varients), it's A4
     123XTCF_CONTROL_BLOCK_OFFSET               EQU     10h     ; ...and for XT-CF (all variants), it's A4
    124124ADP50L_CONTROL_BLOCK_OFFSET             EQU     10h
    125125
Note: See TracChangeset for help on using the changeset viewer.