Changeset 545 in xtideuniversalbios for trunk/XTIDE_Universal_BIOS/Src/Device/IDE/IdeIO.asm

Timestamp:

Apr 19, 2013, 11:44:35 AM (11 years ago)

Author:

aitotat@…

google:author:

aitotat@gmail.com

Message:

Changes to XTIDE Universal BIOS:

• Integrated XT-CFv3 support by James Pearce.
• XT-CFv2 memory mapped I/O and DMA modes are no longer supported (but PIO mode is).

File:

• trunk/XTIDE_Universal_BIOS/Src/Device/IDE/IdeIO.asm (modified) (4 diffs)

trunk/XTIDE_Universal_BIOS/Src/Device/IDE/IdeIO.asm

@@ -52 +52 @@
 ;--------------------------------------------------------------------
 IdeIO_InputToALfromIdeRegisterInDL:
-    xor     dh, dh  ; IDE Register index now in DX
-    mov     bx, dx  ; and BX
+    xor     dh, dh  ; IDE Register index now in DX...
     mov     al, [di+DPT_ATA.bDevice]
     cmp     al, DEVICE_8BIT_XTIDE_REV2
     jb      SHORT .InputToALfromRegisterInDX    ; Standard IDE controllers and XTIDE rev 1
+    mov     bx, dx  ; ...and BX for A0<->A3 swap and for memory mapped I/O
 
 %ifdef MODULE_8BIT_IDE_ADVANCED
@@ -109 +109 @@
     ; At this point remaining controllers (JRIDE, XTCF and ADP50L) all have a control
     ; block offset of 8 or (8<<1) so we add 8 here and do the SHL 1 later if needed.
-    add     dx, 8
+    add     dx, BYTE 8
     cmp     bl, DEVICE_8BIT_JRIDE_ISA
     jb      SHORT IdeIO_OutputALtoIdeRegisterInDL.ShlRegisterIndexInDXandOutputAL   ; All XT-CF modes
@@ -127 +127 @@
     ; a small trick since we only access Device Control Register at
     ; offset 6h: Always clear A3 and set A0.
-    mov     bh, dh  ; Zero BH
+    call    AccessDPT_GetIdevarsToCSBX
     add     dx, [cs:bx+IDEVARS.wControlBlockPort]
     xor     dl, 1001b                       ; Clear A3, Set A0
@@ -134 +134 @@
 
 .OutputALtoControlBlockRegisterInDX:
-    call    AccessDPT_GetIdevarsToCSBX      ; *FIXME* Why is this call here but not in the above block?
+    call    AccessDPT_GetIdevarsToCSBX
     add     dx, [cs:bx+IDEVARS.wControlBlockPort]
     out     dx, al