Changeset 536 in xtideuniversalbios for trunk/XTIDE_Universal_BIOS/Src/Device/IDE/IdeIO.asm


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Timestamp:
Apr 10, 2013, 6:27:15 PM (11 years ago)
Author:
krille_n_@…
google:author:
krille_n_@hotmail.com
Message:

Changes:

  • Added support for the Silicon Valley Computer ADP50L controller (and possibly other IDE controllers from SVC using memory mapped I/O). Please note that this has not been tested in any way since I don't have any of these cards myself (make backups before trying this on drives with important data). Also, *if* it works, make sure it works reliably (stress test the disk system). Some things you should know: 1) Autodetection for this controller has not been added to XTIDECFG, you need to manually select the "SVC ADP50L" controller (and possibly change the BIOS segment address if not using the default of C800h). 2) The memory mapped I/O window is inside the ROM address space of the controller. The XTIDE Universal BIOS currently do not support this so that means you need to use another ROM (for example, an XTIDE or XTCF card or the BOOT ROM of a NIC). This presents another problem, the original ADP50L BIOS needs to be disabled somehow to avoid conflicts. Either pull the ROM chip or disable the BIOS by removing jumper J3. Note, I have no idea if any of this will actually work. It's basically a shot in the dark.
File:
1 edited

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  • trunk/XTIDE_Universal_BIOS/Src/Device/IDE/IdeIO.asm

    r526 r536  
    6161    je      SHORT .ReverseA0andA3fromRegisterIndexInDX
    6262
     63    eSHL_IM dx, 1   ; ADP50L and XT-CF
    6364    cmp     al, DEVICE_8BIT_JRIDE_ISA
    64     jne     SHORT .ShlRegisterIndexInDX         ; All XT-CF modes
    65     ; Fall to .InputToALfromMemoryMappedRegisterInDX
    66 
    67 .InputToALfromMemoryMappedRegisterInDX:
     65    jb      SHORT .InputToALfromRegisterInDX    ; All XT-CF modes
     66    mov     bh, JRIDE_COMMAND_BLOCK_REGISTER_WINDOW_OFFSET >> 8
     67    je      SHORT .InputToALfromMemoryMappedRegisterInBX
     68    mov     bl, dl
     69    mov     bh, ADP50L_COMMAND_BLOCK_REGISTER_WINDOW_OFFSET >> 8
     70
     71.InputToALfromMemoryMappedRegisterInBX:
    6872    push    ds
    69     mov     ds, [di+DPT.wBasePort]  ; Segment for JR-IDE/ISA
    70     mov     al, [bx+JRIDE_COMMAND_BLOCK_REGISTER_WINDOW_OFFSET]
     73    mov     ds, [di+DPT.wBasePort]  ; Segment for JR-IDE/ISA and ADP50L
     74    mov     al, [bx]
    7175    pop     ds
    7276    ret
     
    7579.ReverseA0andA3fromRegisterIndexInDX:
    7680    mov     dl, [cs:bx+g_rgbSwapA0andA3fromIdeRegisterIndex]
    77     SKIP2B  bx  ; Skip shl dx, 1
    78 
    79 .ShlRegisterIndexInDX:
    80     eSHL_IM dx, 1
    81     ; Fall to .InputToALfromRegisterInDX
    8281
    8382.InputToALfromRegisterInDX:
     
    108107    je      SHORT .ReverseA0andA3fromRegisterIndexInDX
    109108
     109    ; At this point remaining controllers (JRIDE, XTCF and ADP50L) all have a control
     110    ; block offset of 8 or (8<<1) so we add 8 here and do the SHL 1 later if needed.
     111    add     dx, 8
    110112    cmp     bl, DEVICE_8BIT_JRIDE_ISA
    111     jne     SHORT .ShlRegisterIndexInDX     ; All XT-CF modes
    112     ; Fall to .OutputALtoMemoryMappedRegisterInDX
    113 
    114 .OutputALtoMemoryMappedRegisterInDX:
    115     mov     bx, JRIDE_CONTROL_BLOCK_REGISTER_WINDOW_OFFSET
    116     jmp     SHORT IdeIO_OutputALtoIdeRegisterInDL.OutputALtoMemoryMappedRegisterInDXwithWindowOffsetInBX
     113    jb      SHORT IdeIO_OutputALtoIdeRegisterInDL.ShlRegisterIndexInDXandOutputAL   ; All XT-CF modes
     114    mov     bx, JRIDE_CONTROL_BLOCK_REGISTER_WINDOW_OFFSET - 8          ; Zeroes BL. -8 compensates for the ADD
     115    je      SHORT IdeIO_OutputALtoIdeRegisterInDL.OutputALtoMemoryMappedRegisterInDXwithWindowOffsetInBX
     116    ; The commented instructions below shows what happens next (saved for clarity) but as an optimization
     117    ; we can accomplish the same thing with this jump.
     118    jmp     SHORT IdeIO_OutputALtoIdeRegisterInDL.ShlDXandMovHighByteOfADP50LoffsetsToBH
     119;   eSHL_IM dx, 1
     120;   mov     bh, (ADP50L_CONTROL_BLOCK_REGISTER_WINDOW_OFFSET - 16) >> 8 ; -16 compensates for the ADD and SHL
     121;   jmp     SHORT IdeIO_OutputALtoIdeRegisterInDL.OutputALtoMemoryMappedRegisterInDXwithWindowOffsetInBX
    117122%endif
    118123
     
    122127    ; a small trick since we only access Device Control Register at
    123128    ; offset 6h: Always clear A3 and set A0.
     129    mov     bh, dh  ; Zero BH
    124130    add     dx, [cs:bx+IDEVARS.wControlBlockPort]
    125131    xor     dl, 1001b                       ; Clear A3, Set A0
    126     jmp     SHORT OutputALtoPortInDX
    127 
    128 .ShlRegisterIndexInDX:
    129     eSHL_IM dx, 1
    130     add     dx, BYTE XTCF_CONTROL_BLOCK_OFFSET
    131     jmp     SHORT OutputALtoRegisterInDX
     132    out     dx, al
     133    ret
    132134
    133135.OutputALtoControlBlockRegisterInDX:
    134     call    AccessDPT_GetIdevarsToCSBX
     136    call    AccessDPT_GetIdevarsToCSBX      ; *FIXME* Why is this call here but not in the above block?
    135137    add     dx, [cs:bx+IDEVARS.wControlBlockPort]
    136     jmp     SHORT OutputALtoPortInDX
     138    out     dx, al
     139    ret
    137140
    138141
     
    160163
    161164    cmp     bl, DEVICE_8BIT_JRIDE_ISA
    162     jne     SHORT .ShlRegisterIndexInDX     ; All XT-CF modes
    163     ; Fall to .OutputALtoMemoryMappedRegisterInDX
    164 
    165 .OutputALtoMemoryMappedRegisterInDX:
    166     mov     bx, JRIDE_COMMAND_BLOCK_REGISTER_WINDOW_OFFSET
     165    jb      SHORT .ShlRegisterIndexInDXandOutputAL  ; All XT-CF modes
     166    mov     bx, JRIDE_COMMAND_BLOCK_REGISTER_WINDOW_OFFSET  ; Zeroes BL
     167    je      SHORT .OutputALtoMemoryMappedRegisterInDXwithWindowOffsetInBX
     168.ShlDXandMovHighByteOfADP50LoffsetsToBH:
     169    eSHL_IM dx, 1
     170    mov     bh, ADP50L_COMMAND_BLOCK_REGISTER_WINDOW_OFFSET >> 8    ; BL is zero so we only need to change BH
     171
    167172.OutputALtoMemoryMappedRegisterInDXwithWindowOffsetInBX:
    168173    add     bx, dx
    169174    push    ds
    170     mov     ds, [di+DPT.wBasePort]  ; Segment for JR-IDE/ISA
     175    mov     ds, [di+DPT.wBasePort]  ; Segment for JR-IDE/ISA and ADP50L
    171176    mov     [bx], al
    172177    pop     ds
     
    177182    mov     bx, dx
    178183    mov     dl, [cs:bx+g_rgbSwapA0andA3fromIdeRegisterIndex]
    179     SKIP2B  bx  ; Skip shl dx, 1
    180 
    181 .ShlRegisterIndexInDX:
     184    SKIP2B  bx  ; Skip eSHL_IM dx, 1
     185
     186.ShlRegisterIndexInDXandOutputAL:
    182187    eSHL_IM dx, 1
    183188    ; Fall to OutputALtoRegisterInDX
     
    186191OutputALtoRegisterInDX:
    187192    add     dx, [di+DPT.wBasePort]
    188 OutputALtoPortInDX:
    189193    out     dx, al
    190194    ret
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