Changeset 501 in xtideuniversalbios for trunk/XTIDE_Universal_BIOS/Src/Device


Ignore:
Timestamp:
Jan 26, 2013, 4:58:50 PM (11 years ago)
Author:
aitotat@…
google:author:
aitotat@gmail.com
Message:

Changes to XTIDE Universal BIOS:

  • XTIDE rev 2 and modded XTIDE rev 1 work again (fixed A0<->A3 swap when accessing Control Block Registers).
  • System INT 13h handler is no longer copied to INT 40h (testing if something uses INT 40h).
  • Removed controller hardware reset: now AH=0h and AH=Dh will only re-initialize drives (SB16 Tertiary and Quaternary IDE should now be safe to use when using Secondary IDE).
Location:
trunk/XTIDE_Universal_BIOS/Src/Device
Files:
3 edited

Legend:

Unmodified
Added
Removed

  • trunk/XTIDE_Universal_BIOS/Src/Device/Device.asm

    r480 r501  
    5555%else                   ; IDE
    5656    Device_FinalizeDPT      EQU     IdeDPT_Finalize
    57 %endif
    58 
    59 
    60 ;--------------------------------------------------------------------
    61 ; Device_ResetMasterAndSlaveController
    62 ;   Parameters:
    63 ;       DS:DI:  Ptr to DPT (in RAMVARS segment)
    64 ;   Returns:
    65 ;       AH:     INT 13h Error Code
    66 ;       CF:     Cleared if success, Set if error
    67 ;   Corrupts registers:
    68 ;       AL, BX, CX, DX
    69 ;--------------------------------------------------------------------
    70 %ifdef MODULE_SERIAL    ; IDE + Serial
    71 Device_ResetMasterAndSlaveController:
    72     TEST_USING_DPT_AND_JUMP_IF_SERIAL_DEVICE    ReturnSuccessForSerialPort
    73     jmp     IdeCommand_ResetMasterAndSlaveController
    74 
    75 %else                   ; IDE
    76     Device_ResetMasterAndSlaveController    EQU     IdeCommand_ResetMasterAndSlaveController
    7757%endif
    7858

  • trunk/XTIDE_Universal_BIOS/Src/Device/IDE/IdeCommand.asm

    r493 r501  
    2020; Section containing code
    2121SECTION .text
    22 
    23 ;--------------------------------------------------------------------
    24 ; IdeCommand_ResetMasterAndSlaveController
    25 ;   Parameters:
    26 ;       DS:DI:  Ptr to DPT (in RAMVARS segment)
    27 ;   Returns:
    28 ;       AH:     INT 13h Error Code
    29 ;       CF:     Cleared if success, Set if error
    30 ;   Corrupts registers:
    31 ;       AL, BX, CX, DX
    32 ;--------------------------------------------------------------------
    33 IdeCommand_ResetMasterAndSlaveController:
    34     ; HSR0: Set_SRST
    35     call    AccessDPT_GetDeviceControlByteToAL
    36     or      al, FLG_DEVCONTROL_SRST | FLG_DEVCONTROL_nIEN   ; Set Reset bit
    37     OUTPUT_AL_TO_IDE_CONTROL_BLOCK_REGISTER     DEVICE_CONTROL_REGISTER_out
    38     mov     ax, HSR0_RESET_WAIT_US
    39     call    Timer_DelayMicrosecondsFromAX
    40 
    41     ; HSR1: Clear_wait
    42     call    AccessDPT_GetDeviceControlByteToAL
    43     or      al, FLG_DEVCONTROL_nIEN
    44     and     al, ~FLG_DEVCONTROL_SRST                        ; Clear reset bit
    45     OUTPUT_AL_TO_IDE_CONTROL_BLOCK_REGISTER     DEVICE_CONTROL_REGISTER_out
    46     mov     ax, HSR1_RESET_WAIT_US
    47     call    Timer_DelayMicrosecondsFromAX
    48 
    49     ; HSR2: Check_status
    50     mov     bx, TIMEOUT_AND_STATUS_TO_WAIT(TIMEOUT_MAXIMUM, FLG_STATUS_BSY)
    51     jmp     IdeWait_PollStatusFlagInBLwithTimeoutInBH
    52 
    5322
    5423;--------------------------------------------------------------------

  • trunk/XTIDE_Universal_BIOS/Src/Device/IDE/IdeIO.asm

    r496 r501  
    7777
    7878.ShlRegisterIndexInDX:
    79     eSHL_IM dx, 1
     79    shl     dx, 1
    8080    ; Fall to .InputToALfromRegisterInDX
    8181
    … …  
    9898;--------------------------------------------------------------------
    9999IdeIO_OutputALtoIdeControlBlockRegisterInDL:
    100     ; Note! We do not need to reverse A0 and A3 for XTIDE rev 2 since
    101     ; the only Control Block Register we access is DEVICE_CONTROL_REGISTER_out
    102     ; at offset 6 (0110b).
    103100    xor     dh, dh  ; IDE Register index now in DX
    104101
    105102    mov     bl, [di+DPT_ATA.bDevice]
    106103    cmp     bl, DEVICE_8BIT_XTIDE_REV2
    107     jbe     SHORT .OutputALtoControlBlockRegisterInDX   ; Standard IDE controllers and XTIDE rev 1
     104    je      SHORT .ReverseA0andA3fromRegisterIndexInDX
     105    jb      SHORT .OutputALtoControlBlockRegisterInDX   ; Standard IDE controllers and XTIDE rev 1
    108106
    109107%ifdef MODULE_8BIT_IDE_ADVANCED
    … …  
    117115%endif
    118116
     117.ReverseA0andA3fromRegisterIndexInDX:
     118    ; We cannot use lookup table since A3 will be always set because
     119    ; Control Block Registers start from Command Block + 8h. We can do
     120    ; a small trick since we only access Device Control Register at
     121    ; offset 6h: Always clear A3 and set A0.
     122    add     dx, [cs:bx+IDEVARS.wControlBlockPort]
     123    xor     dl, 1001b                       ; Clear A3, Set A0
     124    jmp     SHORT OutputALtoPortInDX
     125
    119126.ShlRegisterIndexInDX:
    120127    add     dl, XTCF_CONTROL_BLOCK_OFFSET
    121     eSHL_IM dx, 1
     128    shl     dx, 1
    122129    jmp     SHORT OutputALtoRegisterInDX
    123130
    … …  
    163170    ret
    164171%endif
    165        
     172
    166173.ReverseA0andA3fromRegisterIndexInDX:
    167174    mov     bx, dx
    … …  
    170177
    171178.ShlRegisterIndexInDX:
    172     eSHL_IM dx, 1
     179    shl     dx, 1
    173180    ; Fall to OutputALtoRegisterInDX
    174181
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