Changeset 498 in xtideuniversalbios for trunk/XTIDE_Universal_BIOS_Configurator_v2/Src
- Timestamp:
- Jan 4, 2013, 7:22:04 PM (12 years ago)
- google:author:
- aitotat@gmail.com
- File:
-
- 1 edited
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- Unmodified
- Added
- Removed
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trunk/XTIDE_Universal_BIOS_Configurator_v2/Src/IdeAutodetect.asm
r497 r498 76 76 jnc SHORT .IdeDeviceFound 77 77 78 ; Try to detect 8-bit XT-IDE rev 1 78 ; Try to detect 8-bit XT-IDE rev 1 or rev 2. 79 ; Note that A0<->A3 address swaps Status Register and Alternative 80 ; Status Register addresses. That is why we need another step 81 ; to check is this XT-IDE rev 1 or rev 2. 79 82 shr cx, 1 80 83 call DetectIdeDeviceFromPortDXwithStatusRegOffsetsInBLandCX 81 mov al, DEVICE_8BIT_XTIDE_REV1 82 jnc SHORT .IdeDeviceFound 83 84 ; Try to detect 8-bit XT-IDE rev 2 or modded rev 1 85 ; This doesn't actually work since Status Register and Alternative 86 ; Status Register swap place!!! 87 mov bl, 1110b ; STATUS_REGISTER_in with A0 and A3 swapped 88 mov cl, 0111b 89 call DetectIdeDeviceFromPortDXwithStatusRegOffsetsInBLandCX 90 mov al, DEVICE_8BIT_XTIDE_REV2 84 jc SHORT .SkipRestOfDetection ; No XT-IDE rev 1 or rev 2 found 85 86 ; Now we can be sure that we have XT-IDE rev 1 or rev 2. 87 ; Rev 2 swaps address lines A0 and A3 thus LBA Low Register 88 ; moves from offset 3h to offset Ah. There is no Register at 89 ; offset Ah so if we can write to it and read back, then we 90 ; must have XT-IDE rev 2 or modded rev 1. 91 push dx 92 add dx, BYTE 0Ah ; LBA Low Register for XT-IDE rev 2 93 mov al, DEVICE_8BIT_XTIDE_REV2 ; Our test byte 94 out dx, al ; Output our test byte 95 JMP_DELAY 96 in al, dx ; Read back 97 pop dx 98 cmp al, DEVICE_8BIT_XTIDE_REV2 99 je SHORT .IdeDeviceFound 100 mov al, DEVICE_8BIT_XTIDE_REV1 ; We must have rev 1 101 clc 91 102 .IdeDeviceFound: 92 103 ret … … 193 204 .rgwIdeBasePorts: 194 205 dw IDE_PORT_TO_START_DETECTION ; Must be first 195 ; JR-IDE/ISA (Memory Segment Addresses) 196 dw 0C000h 197 dw 0C400h 198 dw 0C800h 199 dw 0CC00h 200 dw 0D000h 201 dw 0D400h 202 dw 0D800h 203 dw 0DC00h 206 ; Standard IDE 207 dw DEVICE_ATA_PRIMARY_PORT 208 dw DEVICE_ATA_SECONDARY_PORT 209 dw DEVICE_ATA_TERTIARY_PORT 210 dw DEVICE_ATA_QUATERNARY_PORT 204 211 ; 8-bit Devices 205 212 dw 200h … … 219 226 dw 3C0h 220 227 dw 3E0h 221 ; Standard IDE 222 dw DEVICE_ATA_PRIMARY_PORT 223 dw DEVICE_ATA_SECONDARY_PORT 224 dw DEVICE_ATA_TERTIARY_PORT 228 ; JR-IDE/ISA (Memory Segment Addresses) 229 dw 0C000h 230 dw 0C400h 231 dw 0C800h 232 dw 0CC00h 233 dw 0D000h 234 dw 0D400h 235 dw 0D800h 225 236 .wLastIdePort: 226 dw DEVICE_ATA_QUATERNARY_PORT237 dw 0DC00h
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