Changeset 491 in xtideuniversalbios for trunk/XTIDE_Universal_BIOS/Inc/Controllers

Timestamp:

Dec 15, 2012, 2:46:29 PM (12 years ago)

Author:

krille_n_@…

google:author:

krille_n_@hotmail.com

Message:

Changes:

• Added a new define (USE_UNDOC_INTEL) that enables optimizations possible by using undocumented instructions available on all Intel processors and truly compatible clones. AFAIK the only exceptions are the NEC V-series and the Sony CXQ70108 processors so this option should be safe for use on the AT builds.
• Building BIOSDRVS or the BIOS without MODULE_STRINGS_COMPRESSED would fail due to the recent code exclusions so I changed them a bit. Also fixed the mistaken change to Main.asm
• Changed the Tandy specific info in Configuration_FullMode.txt so it matches the info in the Wiki.
• Optimizations and fixes in general.

File:

• trunk/XTIDE_Universal_BIOS/Inc/Controllers/XTCF.inc (modified) (5 diffs)

trunk/XTIDE_Universal_BIOS/Inc/Controllers/XTCF.inc

@@ -5 +5 @@
 
 ;
-; XTIDE Universal BIOS and Associated Tools 
+; XTIDE Universal BIOS and Associated Tools
 ; Copyright (C) 2009-2010 by Tomi Tilli, 2011-2012 by XTIDE Universal BIOS Team.
 ;
@@ -12 +12 @@
 ; the Free Software Foundation; either version 2 of the License, or
 ; (at your option) any later version.
-; 
+;
 ; This program is distributed in the hope that it will be useful,
 ; but WITHOUT ANY WARRANTY; without even the implied warranty of
 ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-; GNU General Public License for more details.      
+; GNU General Public License for more details.
 ; Visit http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
 ;
@@ -34 +34 @@
 ; Possible base addresses. Note that all XT-CF IDE registers are SHL 1 compared
 ; to standard IDE registers.
+XTCF_BASE_PORT_DETECTION_SEED       EQU     140h    ; Not a valid base address but needed for autodetection
 XTCF_BASE_PORT_1                    EQU     200h
 XTCF_BASE_PORT_2                    EQU     240h
@@ -42 +43 @@
 ; XT-CF Control Register (do not SHL 1 these!)
 XTCF_CONTROL_REGISTER               EQU     1Fh
-XTCT_CONTROL_REGISTER_INVERTED_in   EQU     1Eh
+XTCF_CONTROL_REGISTER_INVERTED_in   EQU     1Eh
 
 ; Control Register contents:
@@ -48 +49 @@
 ; Control Register holds high byte from Sector Window segment if >= A0h
 ; (First possible segment for Sector Window is A000h)
-; 
+;
 ; 8-bit PIO transfers (port I/O) are used if Control Register is zero.
 ; Any other value means DMA transfers (using DMA channel 3).