Changeset 411 in xtideuniversalbios for trunk/XTIDE_Universal_BIOS/Inc
- Timestamp:
- Apr 26, 2012, 7:41:59 PM (13 years ago)
- google:author:
- aitotat@gmail.com
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/XTIDE_Universal_BIOS/Inc/CustomDPT.inc
r400 r411 45 45 MASKL_DPT_CHS_SHIFT_COUNT EQU (7<<0) ; Bits 0...2, P-CHS to L-CHS bit shift count (0...4) 46 46 FLGL_DPT_SLAVE EQU FLG_DRVNHEAD_DRV ; (1<<4), Drive is slave drive 47 MASKL_DPT_ADDRESSING_MODE EQU (3<<5) ; Bits 5..6, Addressing Mode (bit 6 == FLG_DRVNHEAD_LBA) 47 MASKL_DPT_ADDRESSING_MODE EQU (3<<ADDRESSING_MODE_FIELD_POSITION) ; Bits 5..6, Addressing Mode (bit 6 == FLG_DRVNHEAD_LBA) 48 %ifdef MODULE_IRQ 48 49 FLGL_DPT_ENABLE_IRQ EQU (1<<7) 50 %endif 49 51 50 52 ; Bit definitions for DPT.bFlagsHigh 51 53 FLGH_DPT_BLOCK_MODE_SUPPORTED EQU (1<<1) ; Use block transfer commands (must be bit 1!) 54 %ifdef MODULE_SERIAL 52 55 FLGH_DPT_SERIAL_DEVICE EQU (1<<2) ; Serial Port Device 56 %endif 57 %ifdef MODULE_IRQ 53 58 FLGH_DPT_INTERRUPT_IN_SERVICE EQU (1<<3) ; Set when waiting for IRQ 59 %endif 60 %ifdef MODULE_FEATURE_SETS 54 61 FLGH_DPT_POWER_MANAGEMENT_SUPPORTED EQU (1<<5) 62 %endif 55 63 56 64 ; IDE device only 65 %ifdef MODULE_ADVANCED_ATA 57 66 FLGH_DPT_IORDY EQU (1<<7) ; Controller and Drive supports IORDY 67 %endif 58 68 59 69 ; Serial device only 70 %ifdef MODULE_SERIAL_FLOPPY 60 71 FLGH_DPT_SERIAL_FLOPPY EQU (1<<4) 61 72 FLGH_DPT_SERIAL_FLOPPY_TYPE_MASK EQU 0e0h 62 73 FLGH_DPT_SERIAL_FLOPPY_TYPE_FIELD_POSITION EQU 5 74 %endif 63 75 64 76 ; Addressing modes for DPT.wFlags … … 67 79 ADDRESSING_MODE_PCHS EQU 1 ; P-CHS Addressing Mode (LARGE in many other BIOSes) 68 80 ADDRESSING_MODE_LBA28 EQU 2 ; 28-bit LBA Addressing Mode 81 %ifdef MODULE_EBIOS 69 82 ADDRESSING_MODE_LBA48 EQU 3 ; 48-bit LBA Addressing Mode 83 %endif 70 84 71 85 … … 89 103 .bInitError resb 1 ; Flags for initialization errors 90 104 endstruc 91 %endif92 105 93 106 ; Flags for DPT_ADVANCED_ATA.bInitError … … 99 112 FLG_INITERROR_FAILED_TO_SET_PIO_MODE EQU (1<<5) 100 113 FLG_INITERROR_FAILED_TO_INITIALIZE_STANDBY_TIMER EQU (1<<6) 114 %endif 101 115 102 116
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