Changeset 158 in xtideuniversalbios for trunk/XTIDE_Universal_BIOS/Inc

Timestamp:

May 2, 2011, 9:41:51 AM (14 years ago)

Author:

Tomi Tilli

google:author:

aitotat

Message:

Changes to XTIDE Universal BIOS:

• Optimized few bytes.

Location:

trunk/XTIDE_Universal_BIOS/Inc

Files:

• CustomDPT.inc (modified) (2 diffs)
• IdeRegisters.inc (modified) (2 diffs)

trunk/XTIDE_Universal_BIOS/Inc/CustomDPT.inc

@@ -8 +8 @@
 struc DPT   ; 8 bytes
     ; General Disk Parameter Table related
-    .wFlags                     resb    2
+    .wFlags:
+    .bFlagsLow                  resb    1
+    .bFlagsHigh                 resb    1
     .bIdevarsOffset             resb    1   ; Offset to IDEVARS for this drive
 
@@ -35 +37 @@
 
 
-; Bit definitions for DPT.wFlags
-MASK_DPT_CHS_SHIFT_COUNT        EQU (7<<0)  ; Bits 0...3, P-CHS to L-CHS bit shift count (0...4)
-FLG_DPT_SLAVE                   EQU FLG_DRVNHEAD_DRV    ; (1<<4), Drive is slave drive
-MASK_DPT_ADDRESSING_MODE        EQU (3<<5)  ; Bits 5..6, Addressing Mode (bit 6 == FLG_DRVNHEAD_LBA)
-FLG_DPT_ENABLE_IRQ              EQU (1<<7)
-FLG_DPT_REVERSED_A0_AND_A3      EQU (1<<8)  ; XTIDE mod, Address lines 0 and 3 reversed
-FLG_DPT_SERIAL_DEVICE           EQU (1<<9)  ; Serial Port Device
-FLG_DPT_BLOCK_MODE_SUPPORTED    EQU (1<<10) ; Use block transfer commands
-FLG_DPT_INTERRUPT_IN_SERVICE    EQU (1<<11) ; Set when waiting for IRQ
-FLG_DPT_RESET_nDRDY             EQU (1<<12) ; Drive ready to accept commands
-FLG_DPT_RESET_nINITPRMS         EQU (1<<13) ; Initialize Device Parameters successfull
-FLG_DPT_RESET_nRECALIBRATE      EQU (1<<14) ; Recalibrate successfull
-FLG_DPT_RESET_nSETBLOCK         EQU (1<<15) ; Initialize Block Mode successfull
-MASK_DPT_RESET                  EQU 0F000h
+; Bit definitions for DPT.bFlagsLow
+MASKL_DPT_CHS_SHIFT_COUNT       EQU (7<<0)  ; Bits 0...3, P-CHS to L-CHS bit shift count (0...4)
+FLGL_DPT_SLAVE                  EQU FLG_DRVNHEAD_DRV    ; (1<<4), Drive is slave drive
+MASKL_DPT_ADDRESSING_MODE       EQU (3<<5)  ; Bits 5..6, Addressing Mode (bit 6 == FLG_DRVNHEAD_LBA)
+FLGL_DPT_ENABLE_IRQ             EQU (1<<7)
+
+; Bit definitions for DPT.bFlagsHigh
+FLGH_DPT_REVERSED_A0_AND_A3     EQU (1<<0)  ; XTIDE mod, Address lines 0 and 3 reversed
+FLGH_DPT_SERIAL_DEVICE          EQU (1<<1)  ; Serial Port Device
+FLGH_DPT_BLOCK_MODE_SUPPORTED   EQU (1<<2)  ; Use block transfer commands
+FLGH_DPT_INTERRUPT_IN_SERVICE   EQU (1<<3)  ; Set when waiting for IRQ
+FLGH_DPT_RESET_nDRDY            EQU (1<<4)  ; Drive ready to accept commands
+FLGH_DPT_RESET_nINITPRMS        EQU (1<<5)  ; Initialize Device Parameters successfull
+FLGH_DPT_RESET_nRECALIBRATE     EQU (1<<6)  ; Recalibrate successfull
+FLGH_DPT_RESET_nSETBLOCK        EQU (1<<7)  ; Initialize Block Mode successfull
+MASKH_DPT_RESET                 EQU 0F0h
 
 ; Addressing modes for DPT.wFlags

trunk/XTIDE_Universal_BIOS/Inc/IdeRegisters.inc

@@ -19 +19 @@
 STATUS_REGISTER_in              EQU     7       ; Read only
 COMMAND_REGISTER_out            EQU     7       ; Write only
-XTIDE_DATA_HIGH_REGISTER        EQU     8       ; Non-standard (actually first Control Block reg)
+;XTIDE_DATA_HIGH_REGISTER       EQU     8       ; Non-standard (actually first Control Block reg)
 
 ; IDE Register offsets from Control Block base port
@@ -58 +58 @@
 ; Bit definitions for IDE Device Control Register
 ; Bit 0 must be zero, unlisted bits are reserved.
-FLG_DEVCONTROL_HOB      EQU     (1<<7)  ; High Order Byte (ATA6+)
+;FLG_DEVCONTROL_HOB     EQU     (1<<7)  ; High Order Byte (ATA6+)
 ;FLG_DEVCONTROL_O8H     EQU     (1<<3)  ; Drive has more than 8 heads (pre-ATA only, 1 on ATA1, reserved on ATA2+)
 FLG_DEVCONTROL_SRST     EQU     (1<<2)  ; Software Reset