source: xtideuniversalbios/trunk/XTIDE_Universal_BIOS/Src/Initialization/Vision.asm@ 372

Last change on this file since 372 was 370, checked in by krille_n_@…, 13 years ago

Changes:

  • Added some missing PIO mode timings to ATA_ID.inc (based on info from ​http://www.singlix.net/specs/cfspc4_0.pdf)
  • Updated Configuration_FullMode.txt but it may need additional changes as the Tandy info doesn't match the wiki.
  • Optimizations.
  • Excluded some unused code from XTIDECFG.
File size: 7.9 KB
Line 
1; Project name : XTIDE Universal BIOS
2; Description : Functions for initializing QDI Vision
3; QD6500 and QD6580 VLB IDE Controllers.
4
5; Section containing code
6SECTION .text
7
8;--------------------------------------------------------------------
9; Vision_DetectAndReturnIDinAXandPortInDXifControllerPresent
10; Parameters:
11; Nothing
12; Returns:
13; AX: ID WORD specific for QDI Vision Controllers
14; (AL = QD65xx Config Register contents)
15; (AH = QDI Vision Controller ID (bits 4...7))
16; DX: Controller port (not IDE port)
17; ZF: Set if controller found
18; Cleared if supported controller not found (AX,DX = undefined)
19; Corrupts registers:
20; Nothing
21;--------------------------------------------------------------------
22Vision_DetectAndReturnIDinAXandPortInDXifControllerPresent:
23 ; Check QD65xx base port
24 mov dx, QD65XX_BASE_PORT
25 in al, QD65XX_BASE_PORT + QD65XX_CONFIG_REGISTER_in
26 call IsConfigRegisterWithIDinAL
27 je SHORT VisionControllerDetected
28
29 ; Check QD65xx alternative base port
30 or dl, QD65XX_ALTERNATIVE_BASE_PORT
31 in al, QD65XX_ALTERNATIVE_BASE_PORT + QD65XX_CONFIG_REGISTER_in
32 ; Fall to IsConfigRegisterWithIDinAL
33
34;--------------------------------------------------------------------
35; IsConfigRegisterWithIDinAL
36; Parameters:
37; AL: Possible QD65xx Config Register contents
38; Returns:
39; AH QDI Vision Controller ID or undefined
40; ZF: Set if controller found
41; Cleared if supported controller not found (AH = undefined)
42; Corrupts registers:
43; Nothing
44;--------------------------------------------------------------------
45IsConfigRegisterWithIDinAL:
46 mov ah, al
47 and al, MASK_QDCONFIG_CONTROLLER_ID
48 cmp al, ID_QD6500 << 4
49 je SHORT VisionControllerDetected
50 cmp al, ID_QD6580 << 4
51 je SHORT VisionControllerDetected
52 cmp al, ID_QD6580_ALTERNATE << 4
53VisionControllerDetected:
54 xchg ah, al
55 ret
56
57
58;--------------------------------------------------------------------
59; Vision_DoesIdePortInBXbelongToControllerWithIDinAX
60; Parameters:
61; AL: QD65xx Config Register contents
62; AH: QDI Vision Controller ID (bits 4...7)
63; BX: IDE Base port to check
64; DX: Vision Controller port
65; Returns:
66; ZF: Set if port belongs to controller
67; Cleared if port belongs to another controller
68; Corrupts registers:
69; Nothing
70;--------------------------------------------------------------------
71Vision_DoesIdePortInBXbelongToControllerWithIDinAX:
72 cmp ah, ID_QD6500 << 4
73 je SHORT .DoesIdePortInDXbelongToQD6500
74
75 ; QD6580 always have Primary IDE at 1F0h
76 ; Secondary IDE at 170h can be enabled or disabled
77 cmp bx, DEVICE_ATA_DEFAULT_PORT
78 je SHORT .ReturnResultInZF
79
80 ; Check if Secondary IDE channel is enabled
81 push ax
82 add dx, BYTE QD6580_CONTROL_REGISTER
83 in al, dx
84 sub dx, BYTE QD6580_CONTROL_REGISTER
85 test al, FLG_QDCONTROL_SECONDARY_DISABLED_in
86 pop ax
87 jz SHORT .CompareBXtoSecondaryIDE
88 ret
89
90 ; QD6500 has only one IDE channel that can be at 1F0h or 170h
91.DoesIdePortInDXbelongToQD6500:
92 test al, FLG_QDCONFIG_PRIMARY_IDE
93 jz SHORT .CompareBXtoSecondaryIDE
94 cmp bx, DEVICE_ATA_DEFAULT_PORT
95 ret
96
97.CompareBXtoSecondaryIDE:
98 cmp bx, DEVICE_ATA_DEFAULT_SECONDARY_PORT
99.ReturnResultInZF:
100 ret
101
102
103;--------------------------------------------------------------------
104; Vision_GetMaxPioModeToAL
105; Parameters:
106; AL: QD65xx Config Register contents
107; AH: QDI Vision Controller ID (bits 4...7)
108; Returns:
109; AL: Max supported PIO mode
110; AH: FLGH_DPT_IORDY if IORDY supported, zero otherwise
111; CF: Set if PIO limit necessary
112; Cleared if no need to limit timings
113; Corrupts registers:
114; (AX if CF cleared)
115; Corrupts registers:
116; Nothing
117;--------------------------------------------------------------------
118Vision_GetMaxPioModeToAL:
119 cmp ah, ID_QD6500 << 4
120 clc
121 jne SHORT .NoNeedToLimitForQD6580
122
123 mov ax, 2 ; Limit to PIO 2 because QD6500 does not support IORDY
124 stc
125.NoNeedToLimitForQD6580:
126 ret
127
128
129;--------------------------------------------------------------------
130; Vision_InitializeWithIDinAHandConfigInAL
131; Parameters:
132; AL: QD65xx Config Register contents
133; AH: QDI Vision Controller ID (bits 4...7)
134; DS:DI: Ptr to DPT for Single or Slave Drive
135; SI: Offset to Master DPT if Slave Drive present
136; Zero if Slave Drive not present
137; Returns:
138; CF: Cleared if success
139; Set if error
140; Corrupts registers:
141; AX, BX, CX, DX, BP
142;--------------------------------------------------------------------
143Vision_InitializeWithIDinAHandConfigInAL:
144 ; QD6580 has a Control Register that needs to be programmed
145 mov dx, [di+DPT_ADVANCED_ATA.wControllerBasePort]
146 cmp ah, ID_QD6500 << 4
147 je SHORT .CalculateTimingForQD6500
148
149 ; Program QD6580 Control Register (not available on QD6500) to
150 ; Enable or Disable Read-Ahead and Post-Write Buffer to match
151 ; jumper setting on the multi I/O card.
152 xor ax, ax
153 add dx, BYTE QD6580_CONTROL_REGISTER
154 in al, dx ; Read to get ATAPI jumper status
155 test al, FLG_QDCONTROL_HDONLY_in
156 eCMOVNZ ah, FLG_QDCONTROL_NONATAPI ; Enable Read-Ahead and Post-Write Buffers
157 or ah, MASK_QDCONTROL_FLAGS_TO_SET
158 mov al, ah
159 out dx, al
160 sub dx, BYTE QD6580_CONTROL_REGISTER
161
162 ; Now we need to determine is the drive connected to the Primary or Secondary channel.
163 ; QD6500 has only one channel that can be Primary at 1F0h or Secondary at 170h.
164 ; QD6580 always has Primary channel at 1F0h. Secondary channel at 170h can be Enabled or Disabled.
165 call AccessDPT_GetIdeBasePortToBX
166 cmp bx, DEVICE_ATA_DEFAULT_PORT
167 je SHORT .CalculateTimingTicksForQD6580 ; Primary Channel so no need to modify DX
168 times 2 inc dx ; Secondary Channel IDE Timing Register
169
170 ; QD6500 and QD6580 require slightly different calculations.
171.CalculateTimingTicksForQD6580:
172 mov bp, QD6580_MAX_ACTIVE_TIME_CLOCKS | (QD6580_MIN_ACTIVE_TIME_CLOCKS << 8)
173 jmp SHORT .CalculateTimingsForQD65xx
174
175.CalculateTimingForQD6500:
176 mov bp, QD6500_MAX_ACTIVE_TIME_CLOCKS | (QD6500_MIN_ACTIVE_TIME_CLOCKS << 8)
177
178 ; We need the PIO Cycle Time in CX to calculate Active and Recovery Times.
179.CalculateTimingsForQD65xx:
180 call AdvAtaInit_SelectSlowestCommonPioTimingsToBXandCXfromDSSIandDSDI
181
182 ; Calculate Active Time value for QD65xx IDE Timing Register
183 call AtaID_GetActiveTimeToAXfromPioModeInBX
184 call ConvertNanosecsFromAXwithLimitsInBPtoRegisterValue
185 xchg bp, ax
186
187 ; Calculate Recovery Time value for QD65xx IDE Timing Register
188 call AtaID_GetRecoveryTimeToAXfromPioModeInBXandCycleTimeInCX
189 mov bx, bp ; Active Time value now in BL
190 mov bp, QD65xx_MAX_RECOVERY_TIME_CLOCKS | (QD65xx_MIN_RECOVERY_TIME_CLOCKS << 8)
191 call ConvertNanosecsFromAXwithLimitsInBPtoRegisterValue
192
193 ; Merge the values to a single byte to output
194 eSHIFT_IM al, POSITON_QD65XXIDE_RECOVERY_TIME, shl
195 or al, bl
196 out dx, al
197 ret ; Return with CF cleared
198
199
200;--------------------------------------------------------------------
201; ConvertNanosecsFromAXwithLimitsInBPtoRegisterValue
202; Parameters:
203; AX: Nanosecs to convert
204; BP: Low Byte: Maximum allowed ticks
205; High Byte: Minimum allowed ticks
206; DS:DI: Ptr to DPT for Single or Slave Drive
207; Returns:
208; AL: Timing value for QD65xx register
209; Corrupts registers:
210; Nothing
211;--------------------------------------------------------------------
212ConvertNanosecsFromAXwithLimitsInBPtoRegisterValue:
213 push cx
214
215 ; Get VLB Cycle Time in nanosecs
216 mov cl, VLB_33MHZ_CYCLE_TIME ; Assume 33 MHz or slower VLB bus
217 test BYTE [di+DPT_ADVANCED_ATA.wControllerID], FLG_QDCONFIG_ID3
218 eCMOVZ cl, VLB_40MHZ_CYCLE_TIME
219
220 ; Convert value in AX to VLB ticks
221 div cl ; AL = VLB ticks
222 inc ax ; Round up
223
224 ; Limit value to QD65xx limits
225 mov cx, bp
226 MAX_U al, ch ; Make sure not below minimum
227 MIN_U al, cl ; Make sure not above maximum
228
229 ; Not done yet, we need to invert the ticks since 0 is the slowest
230 ; value on the timing register
231 sub cl, al
232 xchg ax, cx ; Return in AL
233
234 pop cx
235 ret
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