source: xtideuniversalbios/trunk/XTIDE_Universal_BIOS/Src/Initialization/AdvancedAta/Vision.asm@ 536

Last change on this file since 536 was 534, checked in by aitotat@…, 12 years ago

Changes to XTIDE Universal BIOS:

  • Vision controllers are no longer searched from alternative port (B0h) since Intel PIIX4 south bridge mirrors PIC registers there.
File size: 8.7 KB
Line 
1; Project name : XTIDE Universal BIOS
2; Description : Functions for initializing QDI Vision
3; QD6500 and QD6580 VLB IDE Controllers.
4
5;
6; XTIDE Universal BIOS and Associated Tools
7; Copyright (C) 2009-2010 by Tomi Tilli, 2011-2013 by XTIDE Universal BIOS Team.
8;
9; This program is free software; you can redistribute it and/or modify
10; it under the terms of the GNU General Public License as published by
11; the Free Software Foundation; either version 2 of the License, or
12; (at your option) any later version.
13;
14; This program is distributed in the hope that it will be useful,
15; but WITHOUT ANY WARRANTY; without even the implied warranty of
16; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17; GNU General Public License for more details.
18; Visit http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
19;
20
21; Section containing code
22SECTION .text
23
24;--------------------------------------------------------------------
25; Vision_DetectAndReturnIDinAXandPortInDXifControllerPresent
26; Parameters:
27; Nothing
28; Returns:
29; AX: ID WORD specific for QDI Vision Controllers
30; (AL = QD65xx Config Register contents)
31; (AH = QDI Vision Controller ID (bits 4...7))
32; DX: Controller port (not IDE port)
33; ZF: Set if controller found
34; Cleared if supported controller not found (AX,DX = undefined)
35; Corrupts registers:
36; Nothing
37;--------------------------------------------------------------------
38Vision_DetectAndReturnIDinAXandPortInDXifControllerPresent:
39 ; Check QD65xx base port
40 mov dx, QD65XX_BASE_PORT
41 in al, QD65XX_BASE_PORT + QD65XX_CONFIG_REGISTER_in
42
43%if 0
44 ; Checking alternative base port is currently commented away
45 ; since Intel PIIX4 south bridge mirrors Interrupt Controller registers
46 ; from Axh to Bxh.
47 call IsConfigRegisterWithIDinAL
48 je SHORT VisionControllerDetected
49
50 ; Check QD65xx alternative base port
51 or dl, QD65XX_ALTERNATIVE_BASE_PORT
52 in al, QD65XX_ALTERNATIVE_BASE_PORT + QD65XX_CONFIG_REGISTER_in
53%endif ; 0
54 ; Fall to IsConfigRegisterWithIDinAL
55
56;--------------------------------------------------------------------
57; IsConfigRegisterWithIDinAL
58; Parameters:
59; AL: Possible QD65xx Config Register contents
60; Returns:
61; AH QDI Vision Controller ID or undefined
62; ZF: Set if controller found
63; Cleared if supported controller not found (AH = undefined)
64; Corrupts registers:
65; Nothing
66;--------------------------------------------------------------------
67;IsConfigRegisterWithIDinAL:
68 mov ah, al
69 and al, MASK_QDCONFIG_CONTROLLER_ID
70 cmp al, ID_QD6500 << 4
71 je SHORT VisionControllerDetected
72 cmp al, ID_QD6580 << 4
73 je SHORT VisionControllerDetected
74 cmp al, ID_QD6580_ALTERNATE << 4
75VisionControllerDetected:
76 xchg ah, al
77 ret
78
79
80;--------------------------------------------------------------------
81; Vision_DoesIdePortInBXbelongToControllerWithIDinAX
82; Parameters:
83; AL: QD65xx Config Register contents
84; AH: QDI Vision Controller ID (bits 4...7)
85; BX: IDE Base port to check
86; DX: Vision Controller port
87; Returns:
88; ZF: Set if port belongs to controller
89; Cleared if port belongs to another controller
90; Corrupts registers:
91; Nothing
92;--------------------------------------------------------------------
93Vision_DoesIdePortInBXbelongToControllerWithIDinAX:
94 cmp ah, ID_QD6500 << 4
95 je SHORT .DoesIdePortInDXbelongToQD6500
96
97 ; QD6580 always have Primary IDE at 1F0h
98 ; Secondary IDE at 170h can be enabled or disabled
99 cmp bx, DEVICE_ATA_PRIMARY_PORT
100 je SHORT .ReturnResultInZF
101
102 ; Check if Secondary IDE channel is enabled
103 push ax
104 add dx, BYTE QD6580_CONTROL_REGISTER
105 in al, dx
106 sub dx, BYTE QD6580_CONTROL_REGISTER
107 test al, FLG_QDCONTROL_SECONDARY_DISABLED_in
108 pop ax
109 jz SHORT .CompareBXtoSecondaryIDE
110 ret
111
112 ; QD6500 has only one IDE channel that can be at 1F0h or 170h
113.DoesIdePortInDXbelongToQD6500:
114 test al, FLG_QDCONFIG_PRIMARY_IDE
115 jz SHORT .CompareBXtoSecondaryIDE
116 cmp bx, DEVICE_ATA_PRIMARY_PORT
117 ret
118
119.CompareBXtoSecondaryIDE:
120 cmp bx, DEVICE_ATA_SECONDARY_PORT
121.ReturnResultInZF:
122 ret
123
124
125;--------------------------------------------------------------------
126; Vision_GetMaxPioModeToAL
127; Parameters:
128; AL: QD65xx Config Register contents
129; AH: QDI Vision Controller ID (bits 4...7)
130; Returns:
131; AL: Max supported PIO mode
132; AH: FLGH_DPT_IORDY if IORDY supported, zero otherwise
133; CF: Set if PIO limit necessary
134; Cleared if no need to limit timings
135; Corrupts registers:
136; (AX if CF cleared)
137; Corrupts registers:
138; Nothing
139;--------------------------------------------------------------------
140Vision_GetMaxPioModeToAL:
141 cmp ah, ID_QD6500 << 4
142 clc
143 jne SHORT .NoNeedToLimitForQD6580
144
145 mov ax, 2 ; Limit to PIO 2 because QD6500 does not support IORDY
146 stc
147.NoNeedToLimitForQD6580:
148 ret
149
150
151;--------------------------------------------------------------------
152; Vision_InitializeWithIDinAHandConfigInAL
153; Parameters:
154; AL: QD65xx Config Register contents
155; AH: QDI Vision Controller ID (bits 4...7)
156; DS:DI: Ptr to DPT for Single or Slave Drive
157; SI: Offset to Master DPT if Slave Drive present
158; Zero if Slave Drive not present
159; Returns:
160; CF: Cleared if success
161; Set if error
162; Corrupts registers:
163; AX, BX, CX, DX, BP
164;--------------------------------------------------------------------
165Vision_InitializeWithIDinAHandConfigInAL:
166 ; QD6580 has a Control Register that needs to be programmed
167 mov dx, [di+DPT_ADVANCED_ATA.wControllerBasePort]
168 cmp ah, ID_QD6500 << 4
169 je SHORT .CalculateTimingForQD6500
170
171 ; Program QD6580 Control Register (not available on QD6500) to
172 ; Enable or Disable Read-Ahead and Post-Write Buffer to match
173 ; jumper setting on the multi I/O card.
174 xor ax, ax
175 add dx, BYTE QD6580_CONTROL_REGISTER
176 in al, dx ; Read to get ATAPI jumper status
177 test al, FLG_QDCONTROL_HDONLY_in
178 eCMOVNZ ah, FLG_QDCONTROL_NONATAPI ; Enable Read-Ahead and Post-Write Buffers
179 or ah, MASK_QDCONTROL_FLAGS_TO_SET
180 mov al, ah
181 out dx, al
182 sub dx, BYTE QD6580_CONTROL_REGISTER
183
184 ; Now we need to determine is the drive connected to the Primary or Secondary channel.
185 ; QD6500 has only one channel that can be Primary at 1F0h or Secondary at 170h.
186 ; QD6580 always has Primary channel at 1F0h. Secondary channel at 170h can be Enabled or Disabled.
187 mov bx, [di+DPT.wBasePort]
188 cmp bx, DEVICE_ATA_PRIMARY_PORT
189 je SHORT .CalculateTimingTicksForQD6580 ; Primary Channel so no need to modify DX
190 times 2 inc dx ; Secondary Channel IDE Timing Register
191
192 ; QD6500 and QD6580 require slightly different calculations.
193.CalculateTimingTicksForQD6580:
194 mov bp, QD6580_MAX_ACTIVE_TIME_CLOCKS | (QD6580_MIN_ACTIVE_TIME_CLOCKS << 8)
195 jmp SHORT .CalculateTimingsForQD65xx
196
197.CalculateTimingForQD6500:
198 mov bp, QD6500_MAX_ACTIVE_TIME_CLOCKS | (QD6500_MIN_ACTIVE_TIME_CLOCKS << 8)
199
200 ; We need the PIO Cycle Time in CX to calculate Active and Recovery Times.
201.CalculateTimingsForQD65xx:
202 call AdvAtaInit_SelectSlowestCommonPioTimingsToBXandCXfromDSSIandDSDI
203
204 ; Calculate Active Time value for QD65xx IDE Timing Register
205 call AtaID_GetActiveTimeToAXfromPioModeInBX
206 call ConvertNanosecsFromAXwithLimitsInBPtoRegisterValue
207 xchg bp, ax
208
209 ; Calculate Recovery Time value for QD65xx IDE Timing Register
210 call AtaID_GetRecoveryTimeToAXfromPioModeInBXandCycleTimeInCX
211 mov bx, bp ; Active Time value now in BL
212 mov bp, QD65xx_MAX_RECOVERY_TIME_CLOCKS | (QD65xx_MIN_RECOVERY_TIME_CLOCKS << 8)
213 call ConvertNanosecsFromAXwithLimitsInBPtoRegisterValue
214
215 ; Merge the values to a single byte to output
216 eSHIFT_IM al, POSITON_QD65XXIDE_RECOVERY_TIME, shl
217 or al, bl
218 out dx, al
219 ret ; Return with CF cleared
220
221
222;--------------------------------------------------------------------
223; ConvertNanosecsFromAXwithLimitsInBPtoRegisterValue
224; Parameters:
225; AX: Nanosecs to convert
226; BP: Low Byte: Maximum allowed ticks
227; High Byte: Minimum allowed ticks
228; DS:DI: Ptr to DPT for Single or Slave Drive
229; Returns:
230; AL: Timing value for QD65xx register
231; Corrupts registers:
232; Nothing
233;--------------------------------------------------------------------
234ConvertNanosecsFromAXwithLimitsInBPtoRegisterValue:
235 push cx
236
237 ; Get VLB Cycle Time in nanosecs
238 mov cl, VLB_33MHZ_CYCLE_TIME ; Assume 33 MHz or slower VLB bus
239 test BYTE [di+DPT_ADVANCED_ATA.wControllerID], FLG_QDCONFIG_ID3
240 eCMOVZ cl, VLB_40MHZ_CYCLE_TIME
241
242 ; Convert value in AX to VLB ticks
243 div cl ; AL = VLB ticks
244 inc ax ; Round up
245
246 ; Limit value to QD65xx limits
247 mov cx, bp
248 MAX_U al, ch ; Make sure not below minimum
249 MIN_U al, cl ; Make sure not above maximum
250
251 ; Not done yet, we need to invert the ticks since 0 is the slowest
252 ; value on the timing register
253 sub cl, al
254 xchg ax, cx ; Return in AL
255
256 pop cx
257 ret
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