source: xtideuniversalbios/trunk/XTIDE_Universal_BIOS/Src/Initialization/AdvancedAta/Vision.asm@ 583

Last change on this file since 583 was 582, checked in by krille_n_@…, 10 years ago

Changes:

  • Size optimizations to the QD Vision code.
File size: 8.7 KB
RevLine 
[392]1; Project name : XTIDE Universal BIOS
2; Description : Functions for initializing QDI Vision
3; QD6500 and QD6580 VLB IDE Controllers.
4
5;
[526]6; XTIDE Universal BIOS and Associated Tools
7; Copyright (C) 2009-2010 by Tomi Tilli, 2011-2013 by XTIDE Universal BIOS Team.
[392]8;
9; This program is free software; you can redistribute it and/or modify
10; it under the terms of the GNU General Public License as published by
11; the Free Software Foundation; either version 2 of the License, or
12; (at your option) any later version.
[526]13;
[392]14; This program is distributed in the hope that it will be useful,
15; but WITHOUT ANY WARRANTY; without even the implied warranty of
16; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
[526]17; GNU General Public License for more details.
[392]18; Visit http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
[526]19;
[392]20
21; Section containing code
22SECTION .text
23
24;--------------------------------------------------------------------
25; Vision_DetectAndReturnIDinAXandPortInDXifControllerPresent
26; Parameters:
27; Nothing
28; Returns:
29; AX: ID WORD specific for QDI Vision Controllers
30; (AL = QD65xx Config Register contents)
31; (AH = QDI Vision Controller ID (bits 4...7))
32; DX: Controller port (not IDE port)
33; ZF: Set if controller found
34; Cleared if supported controller not found (AX,DX = undefined)
35; Corrupts registers:
36; Nothing
37;--------------------------------------------------------------------
38Vision_DetectAndReturnIDinAXandPortInDXifControllerPresent:
39 ; Check QD65xx base port
40 mov dx, QD65XX_BASE_PORT
41 in al, QD65XX_BASE_PORT + QD65XX_CONFIG_REGISTER_in
[534]42
[542]43%ifdef DANGEROUS_DETECTION
[534]44 ; Checking alternative base port is currently commented away
45 ; since Intel PIIX4 south bridge mirrors Interrupt Controller registers
46 ; from Axh to Bxh.
[392]47 call IsConfigRegisterWithIDinAL
48 je SHORT VisionControllerDetected
49
50 ; Check QD65xx alternative base port
51 or dl, QD65XX_ALTERNATIVE_BASE_PORT
52 in al, QD65XX_ALTERNATIVE_BASE_PORT + QD65XX_CONFIG_REGISTER_in
[542]53%endif ; DANGEROUS_DETECTION
[392]54 ; Fall to IsConfigRegisterWithIDinAL
55
56;--------------------------------------------------------------------
57; IsConfigRegisterWithIDinAL
58; Parameters:
59; AL: Possible QD65xx Config Register contents
60; Returns:
61; AH QDI Vision Controller ID or undefined
62; ZF: Set if controller found
63; Cleared if supported controller not found (AH = undefined)
64; Corrupts registers:
65; Nothing
66;--------------------------------------------------------------------
[542]67IsConfigRegisterWithIDinAL:
[392]68 mov ah, al
69 and al, MASK_QDCONFIG_CONTROLLER_ID
70 cmp al, ID_QD6500 << 4
71 je SHORT VisionControllerDetected
72 cmp al, ID_QD6580 << 4
73 je SHORT VisionControllerDetected
74 cmp al, ID_QD6580_ALTERNATE << 4
75VisionControllerDetected:
76 xchg ah, al
77 ret
78
79
80;--------------------------------------------------------------------
81; Vision_DoesIdePortInBXbelongToControllerWithIDinAX
82; Parameters:
83; AL: QD65xx Config Register contents
84; AH: QDI Vision Controller ID (bits 4...7)
85; BX: IDE Base port to check
86; DX: Vision Controller port
87; Returns:
88; ZF: Set if port belongs to controller
89; Cleared if port belongs to another controller
90; Corrupts registers:
91; Nothing
92;--------------------------------------------------------------------
93Vision_DoesIdePortInBXbelongToControllerWithIDinAX:
94 cmp ah, ID_QD6500 << 4
95 je SHORT .DoesIdePortInDXbelongToQD6500
96
97 ; QD6580 always have Primary IDE at 1F0h
98 ; Secondary IDE at 170h can be enabled or disabled
[398]99 cmp bx, DEVICE_ATA_PRIMARY_PORT
[392]100 je SHORT .ReturnResultInZF
101
102 ; Check if Secondary IDE channel is enabled
103 push ax
[582]104 push dx
[392]105 add dx, BYTE QD6580_CONTROL_REGISTER
106 in al, dx
107 test al, FLG_QDCONTROL_SECONDARY_DISABLED_in
[582]108 pop dx
[392]109 pop ax
110 jz SHORT .CompareBXtoSecondaryIDE
111 ret
112
113 ; QD6500 has only one IDE channel that can be at 1F0h or 170h
114.DoesIdePortInDXbelongToQD6500:
115 test al, FLG_QDCONFIG_PRIMARY_IDE
116 jz SHORT .CompareBXtoSecondaryIDE
[398]117 cmp bx, DEVICE_ATA_PRIMARY_PORT
[392]118 ret
119
120.CompareBXtoSecondaryIDE:
[398]121 cmp bx, DEVICE_ATA_SECONDARY_PORT
[392]122.ReturnResultInZF:
123 ret
124
125
126;--------------------------------------------------------------------
[564]127; Vision_GetMaxPioModeToALandMinCycleTimeToBX
[392]128; Parameters:
129; AL: QD65xx Config Register contents
130; AH: QDI Vision Controller ID (bits 4...7)
131; Returns:
132; AL: Max supported PIO mode
133; AH: FLGH_DPT_IORDY if IORDY supported, zero otherwise
[582]134; BX: Min PIO Cycle Time (only if ZF set)
135; ZF: Set if PIO limit necessary
[392]136; Cleared if no need to limit timings
137; Corrupts registers:
138; Nothing
139;--------------------------------------------------------------------
[564]140Vision_GetMaxPioModeToALandMinCycleTimeToBX:
[392]141 cmp ah, ID_QD6500 << 4
142 jne SHORT .NoNeedToLimitForQD6580
143
144 mov ax, 2 ; Limit to PIO 2 because QD6500 does not support IORDY
[564]145 mov bx, PIO_2_MIN_CYCLE_TIME_NS
[392]146.NoNeedToLimitForQD6580:
147 ret
148
149
150;--------------------------------------------------------------------
151; Vision_InitializeWithIDinAHandConfigInAL
152; Parameters:
153; AL: QD65xx Config Register contents
154; AH: QDI Vision Controller ID (bits 4...7)
155; DS:DI: Ptr to DPT for Single or Slave Drive
156; SI: Offset to Master DPT if Slave Drive present
157; Zero if Slave Drive not present
158; Returns:
159; CF: Cleared if success
160; Set if error
161; Corrupts registers:
162; AX, BX, CX, DX, BP
163;--------------------------------------------------------------------
164Vision_InitializeWithIDinAHandConfigInAL:
165 ; QD6580 has a Control Register that needs to be programmed
[582]166 cmp ah, ID_QD6500 << 4
[392]167 mov dx, [di+DPT_ADVANCED_ATA.wControllerBasePort]
[582]168 mov bp, QD6500_MAX_ACTIVE_TIME_CLOCKS | (QD6500_MIN_ACTIVE_TIME_CLOCKS << 8) ; Assume QD6500
169 je SHORT .CalculateTimingsForQD65xx
170 mov bp, QD6580_MAX_ACTIVE_TIME_CLOCKS | (QD6580_MIN_ACTIVE_TIME_CLOCKS << 8) ; It's a QD6580
[392]171
172 ; Program QD6580 Control Register (not available on QD6500) to
173 ; Enable or Disable Read-Ahead and Post-Write Buffer to match
174 ; jumper setting on the multi I/O card.
175 add dx, BYTE QD6580_CONTROL_REGISTER
[582]176 in al, dx ; Read to get ATAPI jumper status
[392]177 test al, FLG_QDCONTROL_HDONLY_in
[582]178 mov al, MASK_QDCONTROL_FLAGS_TO_SET
179 eCMOVNZ al, FLG_QDCONTROL_NONATAPI | MASK_QDCONTROL_FLAGS_TO_SET ; Enable Read-Ahead and Post-Write Buffers
[392]180 out dx, al
[582]181 dec dx ; Secondary Channel IDE Timing Register
[392]182
183 ; Now we need to determine is the drive connected to the Primary or Secondary channel.
184 ; QD6500 has only one channel that can be Primary at 1F0h or Secondary at 170h.
185 ; QD6580 always has Primary channel at 1F0h. Secondary channel at 170h can be Enabled or Disabled.
[582]186 cmp BYTE [di+DPT.wBasePort], DEVICE_ATA_SECONDARY_PORT & 0FFh
187 je SHORT .CalculateTimingsForQD65xx ; Secondary Channel so no need to modify DX
188 dec dx
189 dec dx ; Primary Channel IDE Timing Register
[392]190
191 ; We need the PIO Cycle Time in CX to calculate Active and Recovery Times.
192.CalculateTimingsForQD65xx:
193 call AdvAtaInit_SelectSlowestCommonPioTimingsToBXandCXfromDSSIandDSDI
194
195 ; Calculate Active Time value for QD65xx IDE Timing Register
196 call AtaID_GetActiveTimeToAXfromPioModeInBX
197 call ConvertNanosecsFromAXwithLimitsInBPtoRegisterValue
198 xchg bp, ax
199
200 ; Calculate Recovery Time value for QD65xx IDE Timing Register
201 call AtaID_GetRecoveryTimeToAXfromPioModeInBXandCycleTimeInCX
202 mov bx, bp ; Active Time value now in BL
203 mov bp, QD65xx_MAX_RECOVERY_TIME_CLOCKS | (QD65xx_MIN_RECOVERY_TIME_CLOCKS << 8)
204 call ConvertNanosecsFromAXwithLimitsInBPtoRegisterValue
205
206 ; Merge the values to a single byte to output
[566]207 eSHL_IM al, POSITION_QD65XXIDE_RECOVERY_TIME
[392]208 or al, bl
209 out dx, al
210 ret ; Return with CF cleared
211
212
213;--------------------------------------------------------------------
214; ConvertNanosecsFromAXwithLimitsInBPtoRegisterValue
215; Parameters:
216; AX: Nanosecs to convert
217; BP: Low Byte: Maximum allowed ticks
218; High Byte: Minimum allowed ticks
219; DS:DI: Ptr to DPT for Single or Slave Drive
220; Returns:
221; AL: Timing value for QD65xx register
222; Corrupts registers:
223; Nothing
224;--------------------------------------------------------------------
225ConvertNanosecsFromAXwithLimitsInBPtoRegisterValue:
226 push cx
227
228 ; Get VLB Cycle Time in nanosecs
229 mov cl, VLB_33MHZ_CYCLE_TIME ; Assume 33 MHz or slower VLB bus
230 test BYTE [di+DPT_ADVANCED_ATA.wControllerID], FLG_QDCONFIG_ID3
231 eCMOVZ cl, VLB_40MHZ_CYCLE_TIME
232
233 ; Convert value in AX to VLB ticks
234 div cl ; AL = VLB ticks
235 inc ax ; Round up
236
237 ; Limit value to QD65xx limits
238 mov cx, bp
239 MAX_U al, ch ; Make sure not below minimum
240 MIN_U al, cl ; Make sure not above maximum
241
242 ; Not done yet, we need to invert the ticks since 0 is the slowest
243 ; value on the timing register
244 sub cl, al
245 xchg ax, cx ; Return in AL
246
247 pop cx
248 ret
Note: See TracBrowser for help on using the repository browser.