source: xtideuniversalbios/trunk/XTIDE_Universal_BIOS/Src/Device/IDE/IdeIO.asm@ 493

Last change on this file since 493 was 493, checked in by gregli@…, 12 years ago

Separated MODULE_8BIT_IDE into the basic part used by XTIDE rev 1 and rev 2 which is PIO based, and MODULE_8BIT_IDE_ADVANCED for JRIDE and XTCF support which requires memory mapping and/or DMA. This allows for creating an 8KB image with boot menu support (but no hotkeys) for the XTIDE rev 1. Cleaned up how we reset the drive translation information, ensuring it is properly set between boot attempt on a primary and secondary drive - as a result we clean it when needed, rather than trying to always keep it clean. Also fixed translation bugs in int13h.asm where I had previously missed converting some MODULE_HOTKEYS into MODULE_DRIVEXLATE.

File size: 5.8 KB
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1; Project name : XTIDE Universal BIOS
2; Description : IDE Register I/O functions when supporting 8-bit
3; devices that need address translations.
4
5;
6; XTIDE Universal BIOS and Associated Tools
7; Copyright (C) 2009-2010 by Tomi Tilli, 2011-2012 by XTIDE Universal BIOS Team.
8;
9; This program is free software; you can redistribute it and/or modify
10; it under the terms of the GNU General Public License as published by
11; the Free Software Foundation; either version 2 of the License, or
12; (at your option) any later version.
13;
14; This program is distributed in the hope that it will be useful,
15; but WITHOUT ANY WARRANTY; without even the implied warranty of
16; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17; GNU General Public License for more details.
18; Visit http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
19;
20
21; Section containing code
22SECTION .text
23
24;--------------------------------------------------------------------
25; IdeIO_InputStatusRegisterToAL
26; Parameters:
27; DS:DI: Ptr to DPT (in RAMVARS segment)
28; Returns:
29; AL: IDE Status Register contents
30; Corrupts registers:
31; BX, DX
32;--------------------------------------------------------------------
33ALIGN JUMP_ALIGN
34IdeIO_InputStatusRegisterToAL:
35%ifndef MODULE_8BIT_IDE
36 INPUT_TO_AL_FROM_IDE_REGISTER STATUS_REGISTER_in
37 ret
38
39%else
40 mov dl, STATUS_REGISTER_in
41 ; Fall to IdeIO_InputToALfromIdeRegisterInDL
42
43;--------------------------------------------------------------------
44; IdeIO_InputToALfromIdeRegisterInDL
45; Parameters:
46; DL: IDE Register
47; DS:DI: Ptr to DPT (in RAMVARS segment)
48; Returns:
49; AL: Inputted byte
50; Corrupts registers:
51; BX, DX
52;--------------------------------------------------------------------
53IdeIO_InputToALfromIdeRegisterInDL:
54 xor dh, dh ; IDE Register index now in DX
55 mov bx, dx ; and BX
56 mov al, [di+DPT_ATA.bDevice]
57 cmp al, DEVICE_8BIT_XTIDE_REV2
58 je SHORT .ReverseA0andA3fromRegisterIndexInDX
59 jb SHORT .InputToALfromRegisterInDX ; Standard IDE controllers and XTIDE rev 1
60
61%ifdef MODULE_8BIT_IDE_ADVANCED
62 cmp al, DEVICE_8BIT_JRIDE_ISA
63 jne SHORT .ShlRegisterIndexInDX ; All XT-CF modes
64 ; Fall to .InputToALfromMemoryMappedRegisterInDX
65
66.InputToALfromMemoryMappedRegisterInDX:
67 push ds
68 mov ds, [di+DPT.wBasePort] ; Segment for JR-IDE/ISA
69 mov al, [bx+JRIDE_COMMAND_BLOCK_REGISTER_WINDOW_OFFSET]
70 pop ds
71 ret
72%endif
73
74.ReverseA0andA3fromRegisterIndexInDX:
75 mov dl, [cs:bx+g_rgbSwapA0andA3fromIdeRegisterIndex]
76 SKIP2B bx ; Skip shl dx, 1
77
78.ShlRegisterIndexInDX:
79 eSHL_IM dx, 1
80 ; Fall to .InputToALfromRegisterInDX
81
82.InputToALfromRegisterInDX:
83 add dx, [di+DPT.wBasePort]
84 in al, dx
85 ret
86
87
88;--------------------------------------------------------------------
89; IdeIO_OutputALtoIdeControlBlockRegisterInDL
90; Parameters:
91; AL: Byte to output
92; DL: IDE Control Block Register
93; DS:DI: Ptr to DPT (in RAMVARS segment)
94; Returns:
95; Nothing
96; Corrupts registers:
97; BX, DX
98;--------------------------------------------------------------------
99IdeIO_OutputALtoIdeControlBlockRegisterInDL:
100 ; Note! We do not need to reverse A0 and A3 for XTIDE rev 2 since
101 ; the only Control Block Register we access is DEVICE_CONTROL_REGISTER_out
102 ; at offset 6 (0110b).
103 xor dh, dh ; IDE Register index now in DX
104
105 mov bl, [di+DPT_ATA.bDevice]
106 cmp bl, DEVICE_8BIT_XTIDE_REV2
107 jbe SHORT .OutputALtoControlBlockRegisterInDX ; Standard IDE controllers and XTIDE rev 1
108
109%ifdef MODULE_8BIT_IDE_ADVANCED
110 cmp bl, DEVICE_8BIT_JRIDE_ISA
111 jne SHORT .ShlRegisterIndexInDX ; All XT-CF modes
112 ; Fall to .OutputALtoMemoryMappedRegisterInDX
113
114.OutputALtoMemoryMappedRegisterInDX:
115 mov bx, JRIDE_CONTROL_BLOCK_REGISTER_WINDOW_OFFSET
116 jmp SHORT IdeIO_OutputALtoIdeRegisterInDL.OutputALtoMemoryMappedRegisterInDXwithWindowOffsetInBX
117
118.ShlRegisterIndexInDX:
119 add dl, OFFSET_TO_CONTROL_BLOCK_REGISTERS
120 eSHL_IM dx, 1
121 jmp SHORT OutputALtoRegisterInDX
122%endif
123
124.OutputALtoControlBlockRegisterInDX:
125 call AccessDPT_GetIdevarsToCSBX
126 add dx, [cs:bx+IDEVARS.wControlBlockPort]
127 jmp SHORT OutputALtoPortInDX
128
129
130;--------------------------------------------------------------------
131; IdeIO_OutputALtoIdeRegisterInDL
132; Parameters:
133; AL: Byte to output
134; DL: IDE Command Block Register
135; DS:DI: Ptr to DPT (in RAMVARS segment)
136; Returns:
137; Nothing
138; Corrupts registers:
139; BX, DX
140;--------------------------------------------------------------------
141ALIGN JUMP_ALIGN
142IdeIO_OutputALtoIdeRegisterInDL:
143 xor dh, dh ; IDE Register index now in DX
144
145 mov bl, [di+DPT_ATA.bDevice]
146 cmp bl, DEVICE_8BIT_XTIDE_REV2
147 je SHORT .ReverseA0andA3fromRegisterIndexInDX
148 jb SHORT OutputALtoRegisterInDX ; Standard IDE controllers and XTIDE rev 1
149
150%ifdef MODULE_8BIT_IDE_ADVANCED
151 cmp bl, DEVICE_8BIT_JRIDE_ISA
152 jne SHORT .ShlRegisterIndexInDX ; All XT-CF modes
153 ; Fall to .OutputALtoMemoryMappedRegisterInDX
154
155.OutputALtoMemoryMappedRegisterInDX:
156 mov bx, JRIDE_COMMAND_BLOCK_REGISTER_WINDOW_OFFSET
157.OutputALtoMemoryMappedRegisterInDXwithWindowOffsetInBX:
158 add bx, dx
159 push ds
160 mov ds, [di+DPT.wBasePort] ; Segment for JR-IDE/ISA
161 mov [bx], al
162 pop ds
163 ret
164%endif
165
166.ReverseA0andA3fromRegisterIndexInDX:
167 mov bx, dx
168 mov dl, [cs:bx+g_rgbSwapA0andA3fromIdeRegisterIndex]
169 SKIP2B bx ; Skip shl dx, 1
170
171.ShlRegisterIndexInDX:
172 eSHL_IM dx, 1
173 ; Fall to OutputALtoRegisterInDX
174
175ALIGN JUMP_ALIGN
176OutputALtoRegisterInDX:
177 add dx, [di+DPT.wBasePort]
178OutputALtoPortInDX:
179 out dx, al
180 ret
181
182
183
184; A0 <-> A3 lookup table
185g_rgbSwapA0andA3fromIdeRegisterIndex:
186 db 0000b ; <-> 0000b, 0
187 db 1000b ; <-> 0001b, 1
188 db 0010b ; <-> 0010b, 2
189 db 1010b ; <-> 0011b, 3
190 db 0100b ; <-> 0100b, 4
191 db 1100b ; <-> 0101b, 5
192 db 0110b ; <-> 0110b, 6
193 db 1110b ; <-> 0111b, 7
194
195%endif ; MODULE_8BIT_IDE
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