source: xtideuniversalbios/trunk/XTIDE_Universal_BIOS/Src/Device/IDE/IdeIO.asm@ 183

Last change on this file since 183 was 181, checked in by krille_n_@…, 13 years ago

Changes to all parts of the project:

  • Size optimizations.
  • Added a define (EXCLUDE_FROM_XTIDECFG) to exclude unused library code from XTIDECFG.
  • Tried to minimize time spent with interrupts disabled.
  • Some minor attempts to improve speed (reordering instructions etc).
  • Tried to improve readability, did some cleanup and fixed some errors in comments.
File size: 2.5 KB
Line 
1; Project name : XTIDE Universal BIOS
2; Description : IDE Register I/O functions.
3
4; Section containing code
5SECTION .text
6
7;--------------------------------------------------------------------
8; IdeIO_OutputALtoIdeRegisterInDL
9; IdeIO_OutputALtoIdeControlBlockRegisterInDL
10; Parameters:
11; AL: Byte to output
12; DL: IDE Register (IdeIO_OutputALtoIdeRegisterInDL)
13; IDE Control Block Register (IdeIO_OutputALtoIdeControlBlockRegisterInDL)
14; DS:DI: Ptr to DPT (in RAMVARS segment)
15; Returns:
16; Nothing
17; Corrupts registers:
18; BX, DX
19;--------------------------------------------------------------------
20ALIGN JUMP_ALIGN
21IdeIO_OutputALtoIdeRegisterInDL:
22 mov bl, IDEVARS.wPort
23 SKIP2B f ; cmp ax, <next instruction>
24 ; Fall to IdeIO_OutputALtoIdeControlBlockRegisterInDL
25
26IdeIO_OutputALtoIdeControlBlockRegisterInDL:
27 mov bl, IDEVARS.wPortCtrl
28 call GetPortToDXandTranslateA0andA3ifNecessary
29 out dx, al
30 ret
31
32
33;--------------------------------------------------------------------
34; IdeIO_InputToALfromIdeRegisterInDL
35; Parameters:
36; DL: IDE Register
37; DS:DI: Ptr to DPT (in RAMVARS segment)
38; Returns:
39; AL: Inputted byte
40; Corrupts registers:
41; BX, DX
42;--------------------------------------------------------------------
43ALIGN JUMP_ALIGN
44IdeIO_InputToALfromIdeRegisterInDL:
45 mov bl, IDEVARS.wPort
46 call GetPortToDXandTranslateA0andA3ifNecessary
47 in al, dx
48 ret
49
50
51;--------------------------------------------------------------------
52; GetPortToDXandTranslateA0andA3ifNecessary
53; Parameters:
54; BL: Offset to port in IDEVARS (IDEVARS.wPort or IDEVARS.wPortCtrl)
55; DL: IDE Register
56; DS:DI: Ptr to DPT (in RAMVARS segment)
57; Returns:
58; DX: Source/Destination Port
59; Corrupts registers:
60; BX
61;--------------------------------------------------------------------
62ALIGN JUMP_ALIGN
63GetPortToDXandTranslateA0andA3ifNecessary:
64 xor bh, bh
65 xor dh, dh ; DX now has IDE register offset
66 add bl, [di+DPT.bIdevarsOffset] ; CS:BX now points port address
67 add dx, [cs:bx]
68 test BYTE [di+DPT.bFlagsHigh], FLGH_DPT_REVERSED_A0_AND_A3
69 jz SHORT .ReturnPortInDX
70
71 ; Exchange address lines A0 and A3 from DL
72 mov bl, dl
73 mov bh, MASK_A3_AND_A0_ADDRESS_LINES
74 and bh, bl ; BH = 0, 1, 8 or 9, we can ignore 0 and 9
75 jz SHORT .ReturnPortInDX ; Jump out since DH is 0
76 xor bh, MASK_A3_AND_A0_ADDRESS_LINES
77 jz SHORT .ReturnPortInDX ; Jump out since DH was 9
78 and dl, ~MASK_A3_AND_A0_ADDRESS_LINES
79 or dl, bh ; Address lines now reversed
80.ReturnPortInDX:
81 ret
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