source: xtideuniversalbios/trunk/XTIDE_Universal_BIOS/Src/Device/IDE/IdeDmaTransfer.asm@ 479

Last change on this file since 479 was 479, checked in by aitotat@…, 12 years ago

Changes to XTIDE Universal BIOS:

  • Simplified non-working DMA code (same problem continues).
File size: 7.3 KB
Line 
1; Project name : XTIDE Universal BIOS
2; Description : IDE Device DMA transfer functions.
3
4;
5; XTIDE Universal BIOS and Associated Tools
6; Copyright (C) 2009-2010 by Tomi Tilli, 2011-2012 by XTIDE Universal BIOS Team.
7;
8; This program is free software; you can redistribute it and/or modify
9; it under the terms of the GNU General Public License as published by
10; the Free Software Foundation; either version 2 of the License, or
11; (at your option) any later version.
12;
13; This program is distributed in the hope that it will be useful,
14; but WITHOUT ANY WARRANTY; without even the implied warranty of
15; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16; GNU General Public License for more details.
17; Visit http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
18;
19
20; Structure containing variables for DMA transfer functions.
21; This struct must not be larger than IDEPACK without INTPACK.
22struc DMAVARS ; Must not be larger than 9 bytes! See IDEPACK in RamVars.inc.
23 .wTotalBytesXferred resb 2 ; 0-1,
24 .wBytesLeftToXfer resb 2 ; 2-3, 0 = 65536
25 .bbbPhysicalAddress resb 3 ; 4-6,
26 resb 1 ; 7, IDEPACK.bDeviceControl
27endstruc
28
29
30; Section containing code
31SECTION .text
32
33;--------------------------------------------------------------------
34; IdeDmaTransfer_StartWithCommandInAL
35; Parameters:
36; AL: IDE command that was used to start the transfer
37; (all PIO read and write commands including Identify Device)
38; ES:SI: Ptr to data buffer (not normalized)
39; DS:DI: Ptr to DPT (in RAMVARS segment)
40; SS:BP: Ptr to IDEPACK
41; Returns:
42; AH: INT 13h Error Code
43; CX: Number of successfully transferred sectors
44; CF: Cleared if success, Set if error
45; Corrupts registers:
46; AL, BX, DX
47;--------------------------------------------------------------------
48ALIGN JUMP_ALIGN
49IdeDmaTransfer_StartWithCommandInAL:
50 ; Initialize DMAVARS
51 xor cx, cx
52 mov [bp+DMAVARS.wTotalBytesXferred], cx
53 mov ch, [bp+IDEPACK.bSectorCount] ; CX = WORDs to transfer
54 shl cx, 1 ; WORDs to BYTEs, 0 = 65536
55 mov [bp+DMAVARS.wBytesLeftToXfer], cx
56
57 ; Convert Segment:Offset type pointer to physical address
58 xor bx, bx
59 mov cx, es
60%rep 4
61 shl cx, 1
62 rcl bx, 1
63%endrep
64 add cx, si
65 adc bl, bh
66 mov [bp+DMAVARS.bbbPhysicalAddress], cx
67 mov [bp+DMAVARS.bbbPhysicalAddress+2], bl
68
69 ; Calculate bytes for first page
70 neg cx ; Max number of bytes for first page, 0 = 65536
71 MIN_U cx, [bp+DMAVARS.wBytesLeftToXfer]
72
73 ; Are we reading or writing?
74 mov bl, CHANNEL_3 | READ | AUTOINIT_DISABLE | ADDRESS_INCREMENT | DEMAND_MODE ; Assume write command
75 test al, 16 ; Bit 4 is cleared on all the read commands but set on 3 of the 4 write commands
76 jnz SHORT TransferBlockToOrFromXTCF
77 cmp al, COMMAND_WRITE_MULTIPLE
78 je SHORT TransferBlockToOrFromXTCF
79
80 ; Read command
81 mov bl, CHANNEL_3 | WRITE | AUTOINIT_DISABLE | ADDRESS_INCREMENT | DEMAND_MODE
82 ; Fall to TransferBlockToOrFromXTCF
83
84
85;--------------------------------------------------------------------
86; TransferBlockToOrFromXTCF
87; Parameters:
88; BX: Mode byte for DMA Mode Register
89; CX: Bytes in first page
90; DS:DI: Ptr to DPT (in RAMVARS segment)
91; SS:BP: Ptr to DMAVARS
92; Returns:
93; DS:DI: Ptr to DPT (in RAMVARS segment)
94; AH: BIOS Error code
95; CX: Number of successfully transferred sectors
96; CF: 0 if transfer successful
97; 1 if any error
98; Corrupts registers:
99; AL, BX, DX
100;--------------------------------------------------------------------
101TransferBlockToOrFromXTCF:
102 ; 8-bit DMA transfers must be done withing 64k physical page.
103 ; We support maximum of 128 sectors (65536 bytes) per one INT 13h call
104 ; so we might need to separate transfer to 2 separate DMA operations.
105
106 ; Transfer first DMA page
107 call StartDMAtransferForXTCFwithDmaModeInBL
108 jcxz .ReturnNumberOfSectorsXferred ; One page was enough (128 sectors)
109 mov [bp+DMAVARS.wTotalBytesXferred], cx ; Store total BYTEs transferred so far
110
111 ; Get bytes left to transfer for second DMA page
112 mov ax, [bp+DMAVARS.wBytesLeftToXfer]
113 sub ax, cx
114 jz SHORT .ReturnNumberOfSectorsXferred ; Transfer was within 64k page
115
116 ; Increment address
117 xchg cx, ax
118 add [bp+DMAVARS.bbbPhysicalAddress], ax
119 adc [bp+DMAVARS.bbbPhysicalAddress+2], bh ; Never sets CF
120
121 ; Transfer second DMA page if necessary (always less than 64k)
122 call StartDMAtransferForXTCFwithDmaModeInBL
123 add [bp+DMAVARS.wTotalBytesXferred], cx
124
125.ReturnNumberOfSectorsXferred:
126 ; Check errors
127 mov bx, TIMEOUT_AND_STATUS_TO_WAIT(TIMEOUT_DRQ, FLG_STATUS_BSY)
128 call IdeWait_PollStatusFlagInBLwithTimeoutInBH
129 jc SHORT .ErrorInTransfer
130
131 ; Return number of sectors transferred
132 mov cx, [bp+DMAVARS.wTotalBytesXferred]
133 jcxz .FullPageOf128SectorsXferred
134%ifdef USE_186
135 shr cx, 9 ; BYTEs to sectors
136%else
137 xchg cl, ch ; BYTEs to WORDs
138 shr cx, 1 ; WORDs to sectors
139%endif
140 clc
141 ret
142
143.FullPageOf128SectorsXferred:
144 mov cx, 128
145 ret
146
147.ErrorInTransfer:
148 mov cx, 0 ; No way to know how many sectors got transferred
149 ret
150
151
152;--------------------------------------------------------------------
153; StartDMAtransferForXTCFwithDmaModeInBL
154; Parameters:
155; BL: Byte for DMA Mode Register
156; CX: Number of BYTEs to transfer
157; DS:DI: Ptr to DPT (in RAMVARS segment)
158; SS:BP: Ptr to DMAVARS
159; Returns:
160; Nothing
161; Corrupts registers:
162; AL, DX
163;--------------------------------------------------------------------
164ALIGN JUMP_ALIGN
165StartDMAtransferForXTCFwithDmaModeInBL:
166 ; Program 8-bit DMA Controller
167 ; Disable Interrupts and DMA Channel 3 during DMA setup
168 cli ; Disable interrupts
169 mov al, SET_CH3_MASK_BIT
170 out MASK_REGISTER_DMA8_out, al ; Disable DMA Channel 3
171
172 ; Set DMA Mode (read or write using channel 3)
173 mov al, bl
174 out MODE_REGISTER_DMA8_out, al
175
176 ; Set address to DMA controller
177 out CLEAR_FLIPFLOP_DMA8_out, al ; Reset flip-flop to low byte
178 mov ax, [bp+DMAVARS.bbbPhysicalAddress]
179 out BASE_AND_CURRENT_ADDRESS_REGISTER_DMA8_CH3_out, al ; Low byte
180 mov al, ah
181 out BASE_AND_CURRENT_ADDRESS_REGISTER_DMA8_CH3_out, al ; High byte
182 mov al, [bp+DMAVARS.bbbPhysicalAddress+2]
183 out PAGE_DMA8_CH_3, al
184
185 ; Set number of bytes to transfer (DMA controller must be programmed number of bytes - 1)
186 out CLEAR_FLIPFLOP_DMA8_out, al ; Reset flip-flop to low byte
187 mov ax, cx
188 dec ax ; DMA controller is programmed for one byte less
189 out BASE_AND_CURRENT_COUNT_REGISTER_DMA8_CH3_out, al ; Low byte
190 mov al, ah
191 out BASE_AND_CURRENT_COUNT_REGISTER_DMA8_CH3_out, al ; High byte
192
193 ; Enable DMA Channel 3
194 mov al, CLEAR_CH3_MASK_BIT
195 out MASK_REGISTER_DMA8_out, al ; Enable DMA Channel 3
196 sti ; Enable interrupts
197
198
199 ; XT-CF transfers 16 bytes at a time. We need to manually
200 ; start transfer for every block.
201 mov dx, [di+DPT.wBasePort]
202 add dl, XTCF_CONTROL_REGISTER
203ALIGN JUMP_ALIGN
204.TransferNextBlock:
205 mov al, RAISE_DRQ_AND_CLEAR_XTCF_XFER_COUNTER
206 cli ; We want no ISR to read DMA Status Register before we do
207 out dx, al ; Transfer up to 16 bytes to/from XT-CF card
208 ; * Here XT-CF sets CPU to wait states during transfer *
209 in al, STATUS_REGISTER_DMA8_in
210 sti
211 test al, FLG_CH3_HAS_REACHED_TERMINAL_COUNT
212 jz SHORT .TransferNextBlock ; All bytes transferred?
213
214 ; Restore XT-CF to normal operation
215 mov al, XTCF_DMA_MODE
216 out dx, al
217 ret
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