source: xtideuniversalbios/trunk/XTIDE_Universal_BIOS/Src/Device/IDE/IdeDmaBlock.asm@ 562

Last change on this file since 562 was 558, checked in by krille_n_@…, 11 years ago

Changes:

  • Building the BIOS Drive Information Tool now works again.
  • Moved all XT-CF related code to MODULE_8BIT_IDE_ADVANCED. I don't see how an XT-CF card could work without *_ADVANCED anyway but if I'm wrong, feel free to undo this. Note! The autodetection code in XTIDECFG has NOT been changed to reflect this (still relies on MODULE_8BIT_IDE).
  • Optimizations and fixes in general.
File size: 7.9 KB
RevLine 
[480]1; Project name : XTIDE Universal BIOS
[558]2; Description : IDE Read/Write functions for transferring block using DMA.
3; These functions should only be called from IdeTransfer.asm.
4
[551]5; Modified JJP 05-Jun-13
[558]6
[480]7;
8; XTIDE Universal BIOS and Associated Tools
[526]9; Copyright (C) 2009-2010 by Tomi Tilli, 2011-2013 by XTIDE Universal BIOS Team.
[480]10;
11; This program is free software; you can redistribute it and/or modify
12; it under the terms of the GNU General Public License as published by
13; the Free Software Foundation; either version 2 of the License, or
14; (at your option) any later version.
15;
16; This program is distributed in the hope that it will be useful,
17; but WITHOUT ANY WARRANTY; without even the implied warranty of
18; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19; GNU General Public License for more details.
20; Visit http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
21;
22
23; Section containing code
24SECTION .text
25
26;--------------------------------------------------------------------
27; IdeDmaBlock_WriteToXTCF
28; Parameters:
29; CX: Block size in 512 byte sectors
30; DX: XTCF Base Port Address
31; ES:SI: Physical address to buffer to receive data
32; Returns:
33; Nothing
34; Corrupts registers:
35; AX, BX, CX, DX
36;--------------------------------------------------------------------
37ALIGN JUMP_ALIGN
38IdeDmaBlock_WriteToXTCF:
39 xchg si, di
40 mov bl, CHANNEL_3 | READ | AUTOINIT_DISABLE | ADDRESS_INCREMENT | DEMAND_MODE
41 call TransferBlockToOrFromXTCF
42 xchg di, si
43 ret
44
45
46;--------------------------------------------------------------------
47; IdeDmaBlock_ReadFromXTCF
48; Parameters:
49; CX: Block size in 512 byte sectors
50; DX: XTCF Base Port Address
51; ES:DI: Physical address to buffer to receive data
52; Returns:
53; Nothing
54; Corrupts registers:
55; AX, BX, CX, DX
56;--------------------------------------------------------------------
57ALIGN JUMP_ALIGN
58IdeDmaBlock_ReadFromXTCF:
59 mov bl, CHANNEL_3 | WRITE | AUTOINIT_DISABLE | ADDRESS_INCREMENT | DEMAND_MODE
60 ; Fall to TransferBlockToOrFromXTCF
61
62
63;--------------------------------------------------------------------
64; TransferBlockToOrFromXTCF
65; Parameters:
66; BL: Mode byte for DMA Mode Register
67; CX: Block size in 512 byte sectors
68; DX: XTCF Base Port Address
69; ES:DI: Physical address to buffer to receive data
70; Returns:
71; Nothing
72; Corrupts registers:
73; AX, BX, CX, DX
74;--------------------------------------------------------------------
75TransferBlockToOrFromXTCF:
[491]76 ; 8-bit DMA transfers must be done within 64k physical page.
[486]77 ; XT-CF support maximum of 64 sector (32768 bytes) blocks in DMA mode
78 ; so we never need to separate transfer to more than 2 separate DMA operations.
[480]79
[545]80 ; Load XT-CFv3 Control Register port to DX
[480]81 add dl, XTCF_CONTROL_REGISTER
82
[551]83 ; convert sectors in CX to BYTES
[480]84%ifdef USE_186
85 shl cx, 9 ; CX = Block size in BYTEs
86%else
[558]87 xchg cl, ch
[480]88 shl cx, 1
89%endif
[551]90
91 ; Calculate bytes for first page
92 mov ax, di
93 neg ax ; 2s compliment
94
[558]95 ; If DI was zero carry flag will be cleared (and set otherwise)
[551]96 ; When DI is zero only one transfer is required since we've limited the
97 ; XT-CFv3 block size to 32k
[558]98 jnc SHORT .TransferLastDmaPageWithSizeInCX
[551]99
100 ; CF was set, so DI != 0 and we might need one or two transfers
[545]101 cmp cx, ax ; if we won't cross a physical page boundary...
[558]102 jbe SHORT .TransferLastDmaPageWithSizeInCX ; ...perform the transfer in one operation
[480]103
[545]104 ; Calculate how much we can transfer on first and second rounds
[558]105 xchg cx, ax ; CX = BYTEs for first page
106 sub ax, cx ; AX = BYTEs for second page
107 push ax ; Save bytes for second transfer on stack
[480]108
109 ; Transfer first DMA page
110 call StartDMAtransferForXTCFwithDmaModeInBL
111 pop cx ; Pop size for second DMA page
112
113.TransferLastDmaPageWithSizeInCX:
114 ; Fall to StartDMAtransferForXTCFwithDmaModeInBL
115
116
117;--------------------------------------------------------------------
118; StartDMAtransferForXTCFwithDmaModeInBL
[545]119; Updated for XT-CFv3, 11-Apr-13
[480]120; Parameters:
[482]121; BL: Byte for DMA Mode Register
[551]122; CX: Number of BYTEs to transfer (1...32768 since max block size is limited to 64)
[545]123; DX: XT-CFv3 Control Register
124; ES: Bits 3..0 have physical address bits 19..16
125; DI: Physical address bits 15..0
[480]126; Returns:
[545]127; ES:DI updated (CX is added)
[480]128; Corrupts registers:
[558]129; AX, CX
[480]130;--------------------------------------------------------------------
131ALIGN JUMP_ALIGN
132StartDMAtransferForXTCFwithDmaModeInBL:
133 ; Program 8-bit DMA Controller
134 ; Disable Interrupts and DMA Channel 3 during DMA setup
135 mov al, SET_CH3_MASK_BIT
[545]136 cli ; Disable interrupts - programming must be atomic
137 out MASK_REGISTER_DMA8_out, al ; Disable DMA Channel 3
[480]138
139 ; Set DMA Mode (read or write using channel 3)
140 mov al, bl
141 out MODE_REGISTER_DMA8_out, al
142
[545]143 ; Send start address to DMA controller
[480]144 mov ax, es
145 out PAGE_DMA8_CH_3, al
146 mov ax, di
[545]147 out CLEAR_FLIPFLOP_DMA8_out, al ; Reset flip-flop to low byte
[480]148 out BASE_AND_CURRENT_ADDRESS_REGISTER_DMA8_CH3_out, al ; Low byte
149 mov al, ah
150 out BASE_AND_CURRENT_ADDRESS_REGISTER_DMA8_CH3_out, al ; High byte
151
152 ; Set number of bytes to transfer (DMA controller must be programmed number of bytes - 1)
153 mov ax, cx
[545]154 dec ax ; DMA controller is programmed for one byte less
[480]155 out BASE_AND_CURRENT_COUNT_REGISTER_DMA8_CH3_out, al ; Low byte
156 mov al, ah
157 out BASE_AND_CURRENT_COUNT_REGISTER_DMA8_CH3_out, al ; High byte
158
159 ; Enable DMA Channel 3
160 mov al, CLEAR_CH3_MASK_BIT
[545]161 out MASK_REGISTER_DMA8_out, al ; Enable DMA Channel 3
162 sti ; Enable interrupts
[480]163
[558]164 ; Update physical address in ES:DI - since IO might need several calls through this function either from here
165 ; if crossing a physical page boundary, or from IdeTransfer.asm if requested sectors was > PIOVARS.wSectorsInBlock
166 ; We update the pointer here (before the actual transfer) to avoid having to save the byte count on the stack
167 mov ax, es ; copy physical page address to ax
168 add di, cx ; add requested bytes to di
169 adc al, 0 ; and increment physical page address, if required
170 mov es, ax ; and save it back in es
171
[545]172 ; XT-CF transfers 16 bytes at a time. We need to manually start transfer for every block by writing (anything)
173 ; to the XT-CFv3 Control Register, which raises DRQ thereby passing system control to the 8237 DMA controller.
174 ; The XT-CFv3 logic releases DRQ after 16 transfers, thereby handing control back to the CPU and allowing any other IRQs or
175 ; DRQs to be serviced (which, on the PC and PC/XT will include DRAM refresh via DMA channel 0). The 16-byte transfers can
176 ; also be interrupted by the DMA controller raising TC (i.e. when done). Each transfer cannot be otherwise interrupted
177 ; and is therefore atomic (and hence fast).
[480]178
[545]179%if 0 ; Slow DMA code - works by checking 8237 status register after each 16-byte transfer, until it reports TC has been raised.
[558]180ALIGN JUMP_ALIGN
181.TransferNextBlock:
182 cli ; We want no ISR to read DMA Status Register before we do
183 out dx, al ; Transfer up to 16 bytes to/from XT-CF card
184 in al, STATUS_REGISTER_DMA8_in
185 sti
186 test al, FLG_CH3_HAS_REACHED_TERMINAL_COUNT
187 jz SHORT .TransferNextBlock ; All bytes transferred?
188%else ; Fast DMA code - perform computed number of transfers, then check DMA status register to be sure
[545]189 add cx, BYTE 15 ; We'll divide transfers in 16-byte atomic transfers,
190 eSHR_IM cx, 4 ; so include any partial block, which will be terminated
191ALIGN JUMP_ALIGN ; by the DMA controller raising T/C
[486]192.TransferNextDmaBlock:
[545]193 out dx, al ; Transfer up to 16 bytes to/from XT-CF card
194 loop .TransferNextDmaBlock ; dec CX and loop if CX > 0, also adds required wait-state
[486]195 inc cx ; set up CX, in case we need to do an extra iteration
[545]196 in al, STATUS_REGISTER_DMA8_in ; check 8237 DMA controller status flags...
197 test al, FLG_CH3_HAS_REACHED_TERMINAL_COUNT ; ... for channel 3 terminal count
198 jz SHORT .TransferNextDmaBlock ; If not set, get more bytes
[558]199%endif
[486]200
[480]201 ret
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