[480] | 1 | ; Project name : XTIDE Universal BIOS
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[558] | 2 | ; Description : IDE Read/Write functions for transferring block using DMA.
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| 3 | ; These functions should only be called from IdeTransfer.asm.
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| 4 |
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[551] | 5 | ; Modified JJP 05-Jun-13
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[558] | 6 |
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[480] | 7 | ;
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| 8 | ; XTIDE Universal BIOS and Associated Tools
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[526] | 9 | ; Copyright (C) 2009-2010 by Tomi Tilli, 2011-2013 by XTIDE Universal BIOS Team.
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[480] | 10 | ;
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| 11 | ; This program is free software; you can redistribute it and/or modify
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| 12 | ; it under the terms of the GNU General Public License as published by
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| 13 | ; the Free Software Foundation; either version 2 of the License, or
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| 14 | ; (at your option) any later version.
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| 15 | ;
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| 16 | ; This program is distributed in the hope that it will be useful,
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| 17 | ; but WITHOUT ANY WARRANTY; without even the implied warranty of
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| 18 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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| 19 | ; GNU General Public License for more details.
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| 20 | ; Visit http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
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| 21 | ;
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| 22 |
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| 23 | ; Section containing code
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| 24 | SECTION .text
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| 25 |
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| 26 | ;--------------------------------------------------------------------
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| 27 | ; IdeDmaBlock_WriteToXTCF
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| 28 | ; Parameters:
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| 29 | ; CX: Block size in 512 byte sectors
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| 30 | ; DX: XTCF Base Port Address
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| 31 | ; ES:SI: Physical address to buffer to receive data
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| 32 | ; Returns:
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| 33 | ; Nothing
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| 34 | ; Corrupts registers:
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| 35 | ; AX, BX, CX, DX
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| 36 | ;--------------------------------------------------------------------
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| 37 | ALIGN JUMP_ALIGN
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| 38 | IdeDmaBlock_WriteToXTCF:
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| 39 | xchg si, di
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| 40 | mov bl, CHANNEL_3 | READ | AUTOINIT_DISABLE | ADDRESS_INCREMENT | DEMAND_MODE
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| 41 | call TransferBlockToOrFromXTCF
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| 42 | xchg di, si
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| 43 | ret
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| 44 |
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| 45 |
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| 46 | ;--------------------------------------------------------------------
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| 47 | ; IdeDmaBlock_ReadFromXTCF
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| 48 | ; Parameters:
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| 49 | ; CX: Block size in 512 byte sectors
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| 50 | ; DX: XTCF Base Port Address
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| 51 | ; ES:DI: Physical address to buffer to receive data
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| 52 | ; Returns:
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| 53 | ; Nothing
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| 54 | ; Corrupts registers:
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| 55 | ; AX, BX, CX, DX
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| 56 | ;--------------------------------------------------------------------
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| 57 | ALIGN JUMP_ALIGN
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| 58 | IdeDmaBlock_ReadFromXTCF:
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| 59 | mov bl, CHANNEL_3 | WRITE | AUTOINIT_DISABLE | ADDRESS_INCREMENT | DEMAND_MODE
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| 60 | ; Fall to TransferBlockToOrFromXTCF
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| 61 |
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| 62 |
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| 63 | ;--------------------------------------------------------------------
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| 64 | ; TransferBlockToOrFromXTCF
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| 65 | ; Parameters:
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| 66 | ; BL: Mode byte for DMA Mode Register
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| 67 | ; CX: Block size in 512 byte sectors
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| 68 | ; DX: XTCF Base Port Address
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| 69 | ; ES:DI: Physical address to buffer to receive data
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| 70 | ; Returns:
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| 71 | ; Nothing
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| 72 | ; Corrupts registers:
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| 73 | ; AX, BX, CX, DX
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| 74 | ;--------------------------------------------------------------------
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| 75 | TransferBlockToOrFromXTCF:
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[491] | 76 | ; 8-bit DMA transfers must be done within 64k physical page.
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[486] | 77 | ; XT-CF support maximum of 64 sector (32768 bytes) blocks in DMA mode
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| 78 | ; so we never need to separate transfer to more than 2 separate DMA operations.
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[480] | 79 |
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[545] | 80 | ; Load XT-CFv3 Control Register port to DX
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[480] | 81 | add dl, XTCF_CONTROL_REGISTER
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| 82 |
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[551] | 83 | ; convert sectors in CX to BYTES
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[480] | 84 | %ifdef USE_186
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| 85 | shl cx, 9 ; CX = Block size in BYTEs
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| 86 | %else
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[558] | 87 | xchg cl, ch
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[480] | 88 | shl cx, 1
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| 89 | %endif
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[551] | 90 |
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| 91 | ; Calculate bytes for first page
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| 92 | mov ax, di
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| 93 | neg ax ; 2s compliment
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| 94 |
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[558] | 95 | ; If DI was zero carry flag will be cleared (and set otherwise)
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[551] | 96 | ; When DI is zero only one transfer is required since we've limited the
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| 97 | ; XT-CFv3 block size to 32k
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[558] | 98 | jnc SHORT .TransferLastDmaPageWithSizeInCX
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[551] | 99 |
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| 100 | ; CF was set, so DI != 0 and we might need one or two transfers
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[545] | 101 | cmp cx, ax ; if we won't cross a physical page boundary...
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[558] | 102 | jbe SHORT .TransferLastDmaPageWithSizeInCX ; ...perform the transfer in one operation
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[480] | 103 |
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[545] | 104 | ; Calculate how much we can transfer on first and second rounds
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[558] | 105 | xchg cx, ax ; CX = BYTEs for first page
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| 106 | sub ax, cx ; AX = BYTEs for second page
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| 107 | push ax ; Save bytes for second transfer on stack
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[480] | 108 |
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| 109 | ; Transfer first DMA page
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| 110 | call StartDMAtransferForXTCFwithDmaModeInBL
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| 111 | pop cx ; Pop size for second DMA page
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| 112 |
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| 113 | .TransferLastDmaPageWithSizeInCX:
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| 114 | ; Fall to StartDMAtransferForXTCFwithDmaModeInBL
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| 115 |
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| 116 |
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| 117 | ;--------------------------------------------------------------------
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| 118 | ; StartDMAtransferForXTCFwithDmaModeInBL
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[545] | 119 | ; Updated for XT-CFv3, 11-Apr-13
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[480] | 120 | ; Parameters:
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[482] | 121 | ; BL: Byte for DMA Mode Register
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[551] | 122 | ; CX: Number of BYTEs to transfer (1...32768 since max block size is limited to 64)
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[545] | 123 | ; DX: XT-CFv3 Control Register
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| 124 | ; ES: Bits 3..0 have physical address bits 19..16
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| 125 | ; DI: Physical address bits 15..0
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[480] | 126 | ; Returns:
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[545] | 127 | ; ES:DI updated (CX is added)
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[480] | 128 | ; Corrupts registers:
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[558] | 129 | ; AX, CX
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[480] | 130 | ;--------------------------------------------------------------------
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| 131 | ALIGN JUMP_ALIGN
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| 132 | StartDMAtransferForXTCFwithDmaModeInBL:
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| 133 | ; Program 8-bit DMA Controller
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| 134 | ; Disable Interrupts and DMA Channel 3 during DMA setup
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| 135 | mov al, SET_CH3_MASK_BIT
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[545] | 136 | cli ; Disable interrupts - programming must be atomic
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| 137 | out MASK_REGISTER_DMA8_out, al ; Disable DMA Channel 3
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[480] | 138 |
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| 139 | ; Set DMA Mode (read or write using channel 3)
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| 140 | mov al, bl
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| 141 | out MODE_REGISTER_DMA8_out, al
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| 142 |
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[545] | 143 | ; Send start address to DMA controller
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[480] | 144 | mov ax, es
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| 145 | out PAGE_DMA8_CH_3, al
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| 146 | mov ax, di
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[545] | 147 | out CLEAR_FLIPFLOP_DMA8_out, al ; Reset flip-flop to low byte
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[480] | 148 | out BASE_AND_CURRENT_ADDRESS_REGISTER_DMA8_CH3_out, al ; Low byte
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| 149 | mov al, ah
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| 150 | out BASE_AND_CURRENT_ADDRESS_REGISTER_DMA8_CH3_out, al ; High byte
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| 151 |
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| 152 | ; Set number of bytes to transfer (DMA controller must be programmed number of bytes - 1)
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| 153 | mov ax, cx
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[545] | 154 | dec ax ; DMA controller is programmed for one byte less
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[480] | 155 | out BASE_AND_CURRENT_COUNT_REGISTER_DMA8_CH3_out, al ; Low byte
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| 156 | mov al, ah
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| 157 | out BASE_AND_CURRENT_COUNT_REGISTER_DMA8_CH3_out, al ; High byte
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| 158 |
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| 159 | ; Enable DMA Channel 3
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| 160 | mov al, CLEAR_CH3_MASK_BIT
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[545] | 161 | out MASK_REGISTER_DMA8_out, al ; Enable DMA Channel 3
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| 162 | sti ; Enable interrupts
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[480] | 163 |
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[558] | 164 | ; Update physical address in ES:DI - since IO might need several calls through this function either from here
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| 165 | ; if crossing a physical page boundary, or from IdeTransfer.asm if requested sectors was > PIOVARS.wSectorsInBlock
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| 166 | ; We update the pointer here (before the actual transfer) to avoid having to save the byte count on the stack
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| 167 | mov ax, es ; copy physical page address to ax
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| 168 | add di, cx ; add requested bytes to di
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| 169 | adc al, 0 ; and increment physical page address, if required
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| 170 | mov es, ax ; and save it back in es
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| 171 |
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[545] | 172 | ; XT-CF transfers 16 bytes at a time. We need to manually start transfer for every block by writing (anything)
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| 173 | ; to the XT-CFv3 Control Register, which raises DRQ thereby passing system control to the 8237 DMA controller.
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| 174 | ; The XT-CFv3 logic releases DRQ after 16 transfers, thereby handing control back to the CPU and allowing any other IRQs or
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| 175 | ; DRQs to be serviced (which, on the PC and PC/XT will include DRAM refresh via DMA channel 0). The 16-byte transfers can
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| 176 | ; also be interrupted by the DMA controller raising TC (i.e. when done). Each transfer cannot be otherwise interrupted
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| 177 | ; and is therefore atomic (and hence fast).
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[480] | 178 |
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[545] | 179 | %if 0 ; Slow DMA code - works by checking 8237 status register after each 16-byte transfer, until it reports TC has been raised.
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[558] | 180 | ALIGN JUMP_ALIGN
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| 181 | .TransferNextBlock:
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| 182 | cli ; We want no ISR to read DMA Status Register before we do
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| 183 | out dx, al ; Transfer up to 16 bytes to/from XT-CF card
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| 184 | in al, STATUS_REGISTER_DMA8_in
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| 185 | sti
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| 186 | test al, FLG_CH3_HAS_REACHED_TERMINAL_COUNT
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| 187 | jz SHORT .TransferNextBlock ; All bytes transferred?
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| 188 | %else ; Fast DMA code - perform computed number of transfers, then check DMA status register to be sure
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[545] | 189 | add cx, BYTE 15 ; We'll divide transfers in 16-byte atomic transfers,
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| 190 | eSHR_IM cx, 4 ; so include any partial block, which will be terminated
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| 191 | ALIGN JUMP_ALIGN ; by the DMA controller raising T/C
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[486] | 192 | .TransferNextDmaBlock:
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[545] | 193 | out dx, al ; Transfer up to 16 bytes to/from XT-CF card
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| 194 | loop .TransferNextDmaBlock ; dec CX and loop if CX > 0, also adds required wait-state
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[486] | 195 | inc cx ; set up CX, in case we need to do an extra iteration
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[545] | 196 | in al, STATUS_REGISTER_DMA8_in ; check 8237 DMA controller status flags...
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| 197 | test al, FLG_CH3_HAS_REACHED_TERMINAL_COUNT ; ... for channel 3 terminal count
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| 198 | jz SHORT .TransferNextDmaBlock ; If not set, get more bytes
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[558] | 199 | %endif
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[486] | 200 |
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[480] | 201 | ret
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