[480] | 1 | ; Project name : XTIDE Universal BIOS |
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| 2 | ; Description : IDE Read/Write functions for transferring |
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[551] | 3 | ; block using DMA. |
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| 4 | ; These functions should only be called from IdeTransfer.asm. |
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| 5 | ; Modified JJP 05-Jun-13 |
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[480] | 6 | ; |
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| 7 | ; XTIDE Universal BIOS and Associated Tools |
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[526] | 8 | ; Copyright (C) 2009-2010 by Tomi Tilli, 2011-2013 by XTIDE Universal BIOS Team. |
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[480] | 9 | ; |
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| 10 | ; This program is free software; you can redistribute it and/or modify |
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| 11 | ; it under the terms of the GNU General Public License as published by |
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| 12 | ; the Free Software Foundation; either version 2 of the License, or |
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| 13 | ; (at your option) any later version. |
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| 14 | ; |
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| 15 | ; This program is distributed in the hope that it will be useful, |
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| 16 | ; but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 17 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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| 18 | ; GNU General Public License for more details. |
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| 19 | ; Visit http://www.gnu.org/licenses/old-licenses/gpl-2.0.html |
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| 20 | ; |
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| 21 | |
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| 22 | ; Section containing code |
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| 23 | SECTION .text |
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| 24 | |
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| 25 | ;-------------------------------------------------------------------- |
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| 26 | ; IdeDmaBlock_WriteToXTCF |
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| 27 | ; Parameters: |
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| 28 | ; CX: Block size in 512 byte sectors |
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| 29 | ; DX: XTCF Base Port Address |
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| 30 | ; ES:SI: Physical address to buffer to receive data |
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| 31 | ; Returns: |
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| 32 | ; Nothing |
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| 33 | ; Corrupts registers: |
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| 34 | ; AX, BX, CX, DX |
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| 35 | ;-------------------------------------------------------------------- |
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| 36 | ALIGN JUMP_ALIGN |
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| 37 | IdeDmaBlock_WriteToXTCF: |
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| 38 | xchg si, di |
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| 39 | mov bl, CHANNEL_3 | READ | AUTOINIT_DISABLE | ADDRESS_INCREMENT | DEMAND_MODE |
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| 40 | call TransferBlockToOrFromXTCF |
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| 41 | xchg di, si |
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| 42 | ret |
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| 43 | |
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| 44 | |
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| 45 | ;-------------------------------------------------------------------- |
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| 46 | ; IdeDmaBlock_ReadFromXTCF |
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| 47 | ; Parameters: |
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| 48 | ; CX: Block size in 512 byte sectors |
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| 49 | ; DX: XTCF Base Port Address |
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| 50 | ; ES:DI: Physical address to buffer to receive data |
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| 51 | ; Returns: |
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| 52 | ; Nothing |
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| 53 | ; Corrupts registers: |
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| 54 | ; AX, BX, CX, DX |
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| 55 | ;-------------------------------------------------------------------- |
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| 56 | ALIGN JUMP_ALIGN |
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| 57 | IdeDmaBlock_ReadFromXTCF: |
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| 58 | mov bl, CHANNEL_3 | WRITE | AUTOINIT_DISABLE | ADDRESS_INCREMENT | DEMAND_MODE |
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| 59 | ; Fall to TransferBlockToOrFromXTCF |
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| 60 | |
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| 61 | |
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| 62 | ;-------------------------------------------------------------------- |
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| 63 | ; TransferBlockToOrFromXTCF |
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| 64 | ; Parameters: |
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| 65 | ; BL: Mode byte for DMA Mode Register |
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| 66 | ; CX: Block size in 512 byte sectors |
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| 67 | ; DX: XTCF Base Port Address |
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| 68 | ; ES:DI: Physical address to buffer to receive data |
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| 69 | ; Returns: |
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| 70 | ; Nothing |
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| 71 | ; Corrupts registers: |
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| 72 | ; AX, BX, CX, DX |
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| 73 | ;-------------------------------------------------------------------- |
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| 74 | TransferBlockToOrFromXTCF: |
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[491] | 75 | ; 8-bit DMA transfers must be done within 64k physical page. |
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[486] | 76 | ; XT-CF support maximum of 64 sector (32768 bytes) blocks in DMA mode |
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| 77 | ; so we never need to separate transfer to more than 2 separate DMA operations. |
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[480] | 78 | |
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[545] | 79 | ; Load XT-CFv3 Control Register port to DX |
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[480] | 80 | add dl, XTCF_CONTROL_REGISTER |
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| 81 | |
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[551] | 82 | ; convert sectors in CX to BYTES |
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[480] | 83 | %ifdef USE_186 |
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| 84 | shl cx, 9 ; CX = Block size in BYTEs |
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| 85 | %else |
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[551] | 86 | xchg cl, ch |
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[480] | 87 | shl cx, 1 |
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| 88 | %endif |
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[551] | 89 | |
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| 90 | ; Calculate bytes for first page |
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| 91 | mov ax, di |
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| 92 | neg ax ; 2s compliment |
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| 93 | |
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| 94 | ; if DI was zero carry flag will be cleared (and set otherwise) |
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| 95 | ; When DI is zero only one transfer is required since we've limited the |
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| 96 | ; XT-CFv3 block size to 32k |
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| 97 | jnc .TransferLastDmaPageWithSizeInCX |
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| 98 | |
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| 99 | ; CF was set, so DI != 0 and we might need one or two transfers |
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[545] | 100 | cmp cx, ax ; if we won't cross a physical page boundary... |
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[551] | 101 | jbe SHORT .TransferLastDmaPageWithSizeInCX ; ...perform the transfer in one operation |
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[480] | 102 | |
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[545] | 103 | ; Calculate how much we can transfer on first and second rounds |
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[551] | 104 | xchg cx, ax ; CX = BYTEs for first page |
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| 105 | sub ax, cx ; AX = BYTEs for second page |
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| 106 | push ax ; Save bytes for second transfer on stack |
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[480] | 107 | |
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| 108 | ; Transfer first DMA page |
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| 109 | call StartDMAtransferForXTCFwithDmaModeInBL |
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| 110 | pop cx ; Pop size for second DMA page |
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| 111 | |
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| 112 | .TransferLastDmaPageWithSizeInCX: |
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| 113 | ; Fall to StartDMAtransferForXTCFwithDmaModeInBL |
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| 114 | |
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| 115 | |
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| 116 | ;-------------------------------------------------------------------- |
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| 117 | ; StartDMAtransferForXTCFwithDmaModeInBL |
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[545] | 118 | ; Updated for XT-CFv3, 11-Apr-13 |
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[480] | 119 | ; Parameters: |
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[482] | 120 | ; BL: Byte for DMA Mode Register |
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[551] | 121 | ; CX: Number of BYTEs to transfer (1...32768 since max block size is limited to 64) |
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[545] | 122 | ; DX: XT-CFv3 Control Register |
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| 123 | ; ES: Bits 3..0 have physical address bits 19..16 |
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| 124 | ; DI: Physical address bits 15..0 |
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[480] | 125 | ; Returns: |
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[545] | 126 | ; ES:DI updated (CX is added) |
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[480] | 127 | ; Corrupts registers: |
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| 128 | ; AX |
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| 129 | ;-------------------------------------------------------------------- |
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| 130 | ALIGN JUMP_ALIGN |
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| 131 | StartDMAtransferForXTCFwithDmaModeInBL: |
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| 132 | ; Program 8-bit DMA Controller |
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| 133 | ; Disable Interrupts and DMA Channel 3 during DMA setup |
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| 134 | mov al, SET_CH3_MASK_BIT |
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[545] | 135 | cli ; Disable interrupts - programming must be atomic |
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| 136 | out MASK_REGISTER_DMA8_out, al ; Disable DMA Channel 3 |
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[480] | 137 | |
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| 138 | ; Set DMA Mode (read or write using channel 3) |
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| 139 | mov al, bl |
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| 140 | out MODE_REGISTER_DMA8_out, al |
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| 141 | |
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[545] | 142 | ; Send start address to DMA controller |
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[480] | 143 | mov ax, es |
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| 144 | out PAGE_DMA8_CH_3, al |
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| 145 | mov ax, di |
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[545] | 146 | out CLEAR_FLIPFLOP_DMA8_out, al ; Reset flip-flop to low byte |
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[480] | 147 | out BASE_AND_CURRENT_ADDRESS_REGISTER_DMA8_CH3_out, al ; Low byte |
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| 148 | mov al, ah |
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| 149 | out BASE_AND_CURRENT_ADDRESS_REGISTER_DMA8_CH3_out, al ; High byte |
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| 150 | |
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| 151 | ; Set number of bytes to transfer (DMA controller must be programmed number of bytes - 1) |
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| 152 | mov ax, cx |
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[545] | 153 | dec ax ; DMA controller is programmed for one byte less |
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[480] | 154 | out BASE_AND_CURRENT_COUNT_REGISTER_DMA8_CH3_out, al ; Low byte |
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| 155 | mov al, ah |
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| 156 | out BASE_AND_CURRENT_COUNT_REGISTER_DMA8_CH3_out, al ; High byte |
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| 157 | |
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| 158 | ; Enable DMA Channel 3 |
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| 159 | mov al, CLEAR_CH3_MASK_BIT |
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[545] | 160 | out MASK_REGISTER_DMA8_out, al ; Enable DMA Channel 3 |
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| 161 | sti ; Enable interrupts |
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[480] | 162 | |
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[545] | 163 | ; XT-CF transfers 16 bytes at a time. We need to manually start transfer for every block by writing (anything) |
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| 164 | ; to the XT-CFv3 Control Register, which raises DRQ thereby passing system control to the 8237 DMA controller. |
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| 165 | ; The XT-CFv3 logic releases DRQ after 16 transfers, thereby handing control back to the CPU and allowing any other IRQs or |
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| 166 | ; DRQs to be serviced (which, on the PC and PC/XT will include DRAM refresh via DMA channel 0). The 16-byte transfers can |
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| 167 | ; also be interrupted by the DMA controller raising TC (i.e. when done). Each transfer cannot be otherwise interrupted |
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| 168 | ; and is therefore atomic (and hence fast). |
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[480] | 169 | |
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[545] | 170 | %if 0 ; Slow DMA code - works by checking 8237 status register after each 16-byte transfer, until it reports TC has been raised. |
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| 171 | ;ALIGN JUMP_ALIGN |
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| 172 | ;.TransferNextBlock: |
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| 173 | ; cli ; We want no ISR to read DMA Status Register before we do |
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| 174 | ; out dx, al ; Transfer up to 16 bytes to/from XT-CF card |
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| 175 | ; in al, STATUS_REGISTER_DMA8_in |
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| 176 | ; sti |
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| 177 | ; test al, FLG_CH3_HAS_REACHED_TERMINAL_COUNT |
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| 178 | ; jz SHORT .TransferNextBlock ; All bytes transferred? |
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[486] | 179 | %endif ; Slow DMA code |
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[480] | 180 | |
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[545] | 181 | %if 1 ; Fast DMA code - perform computed number of transfers, then check DMA status register to be sure |
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| 182 | push cx ; need byte count to update pointer at the end |
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| 183 | add cx, BYTE 15 ; We'll divide transfers in 16-byte atomic transfers, |
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| 184 | eSHR_IM cx, 4 ; so include any partial block, which will be terminated |
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| 185 | ALIGN JUMP_ALIGN ; by the DMA controller raising T/C |
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[486] | 186 | .TransferNextDmaBlock: |
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[545] | 187 | out dx, al ; Transfer up to 16 bytes to/from XT-CF card |
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| 188 | loop .TransferNextDmaBlock ; dec CX and loop if CX > 0, also adds required wait-state |
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[486] | 189 | inc cx ; set up CX, in case we need to do an extra iteration |
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[545] | 190 | in al, STATUS_REGISTER_DMA8_in ; check 8237 DMA controller status flags... |
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| 191 | test al, FLG_CH3_HAS_REACHED_TERMINAL_COUNT ; ... for channel 3 terminal count |
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| 192 | jz SHORT .TransferNextDmaBlock ; If not set, get more bytes |
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| 193 | pop cx ; get back requested bytes |
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[486] | 194 | %endif ; Fast DMA code |
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| 195 | |
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[545] | 196 | ; Update physical address in ES:DI - since IO might need several calls through this function either from here |
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| 197 | ; if crossing a physical page boundary, and from IdeTransfer.asm if requested sectors was > PIOVARS.wSectorsInBlock |
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| 198 | mov ax, es ; copy physical page address to ax |
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| 199 | add di, cx ; add requested bytes to di |
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| 200 | adc al, 0 ; and increment physical page address, if required |
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| 201 | mov es, ax ; and save it back in es |
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[486] | 202 | |
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[480] | 203 | ret |
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