[480] | 1 | ; Project name : XTIDE Universal BIOS |
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| 2 | ; Description : IDE Read/Write functions for transferring |
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| 3 | ; block using DMA. |
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| 4 | ; These functions should only be called from IdeTransfer.asm. |
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| 5 | |
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| 6 | ; |
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| 7 | ; XTIDE Universal BIOS and Associated Tools |
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[526] | 8 | ; Copyright (C) 2009-2010 by Tomi Tilli, 2011-2013 by XTIDE Universal BIOS Team. |
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[480] | 9 | ; |
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| 10 | ; This program is free software; you can redistribute it and/or modify |
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| 11 | ; it under the terms of the GNU General Public License as published by |
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| 12 | ; the Free Software Foundation; either version 2 of the License, or |
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| 13 | ; (at your option) any later version. |
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| 14 | ; |
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| 15 | ; This program is distributed in the hope that it will be useful, |
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| 16 | ; but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 17 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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| 18 | ; GNU General Public License for more details. |
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| 19 | ; Visit http://www.gnu.org/licenses/old-licenses/gpl-2.0.html |
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| 20 | ; |
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| 21 | |
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| 22 | |
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| 23 | ; Section containing code |
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| 24 | SECTION .text |
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| 25 | |
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| 26 | ;-------------------------------------------------------------------- |
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| 27 | ; IdeDmaBlock_WriteToXTCF |
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| 28 | ; Parameters: |
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| 29 | ; CX: Block size in 512 byte sectors |
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| 30 | ; DX: XTCF Base Port Address |
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| 31 | ; ES:SI: Physical address to buffer to receive data |
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| 32 | ; Returns: |
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| 33 | ; Nothing |
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| 34 | ; Corrupts registers: |
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| 35 | ; AX, BX, CX, DX |
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| 36 | ;-------------------------------------------------------------------- |
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| 37 | ALIGN JUMP_ALIGN |
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| 38 | IdeDmaBlock_WriteToXTCF: |
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| 39 | xchg si, di |
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| 40 | mov bl, CHANNEL_3 | READ | AUTOINIT_DISABLE | ADDRESS_INCREMENT | DEMAND_MODE |
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| 41 | call TransferBlockToOrFromXTCF |
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| 42 | xchg di, si |
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| 43 | ret |
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| 44 | |
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| 45 | |
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| 46 | ;-------------------------------------------------------------------- |
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| 47 | ; IdeDmaBlock_ReadFromXTCF |
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| 48 | ; Parameters: |
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| 49 | ; CX: Block size in 512 byte sectors |
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| 50 | ; DX: XTCF Base Port Address |
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| 51 | ; ES:DI: Physical address to buffer to receive data |
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| 52 | ; Returns: |
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| 53 | ; Nothing |
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| 54 | ; Corrupts registers: |
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| 55 | ; AX, BX, CX, DX |
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| 56 | ;-------------------------------------------------------------------- |
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| 57 | ALIGN JUMP_ALIGN |
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| 58 | IdeDmaBlock_ReadFromXTCF: |
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| 59 | mov bl, CHANNEL_3 | WRITE | AUTOINIT_DISABLE | ADDRESS_INCREMENT | DEMAND_MODE |
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| 60 | ; Fall to TransferBlockToOrFromXTCF |
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| 61 | |
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| 62 | |
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| 63 | ;-------------------------------------------------------------------- |
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| 64 | ; TransferBlockToOrFromXTCF |
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| 65 | ; Parameters: |
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| 66 | ; BL: Mode byte for DMA Mode Register |
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| 67 | ; CX: Block size in 512 byte sectors |
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| 68 | ; DX: XTCF Base Port Address |
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| 69 | ; ES:DI: Physical address to buffer to receive data |
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| 70 | ; Returns: |
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| 71 | ; Nothing |
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| 72 | ; Corrupts registers: |
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| 73 | ; AX, BX, CX, DX |
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| 74 | ;-------------------------------------------------------------------- |
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| 75 | TransferBlockToOrFromXTCF: |
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[491] | 76 | ; 8-bit DMA transfers must be done within 64k physical page. |
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[486] | 77 | ; XT-CF support maximum of 64 sector (32768 bytes) blocks in DMA mode |
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| 78 | ; so we never need to separate transfer to more than 2 separate DMA operations. |
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[480] | 79 | |
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[545] | 80 | ; Load XT-CFv3 Control Register port to DX |
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[480] | 81 | add dl, XTCF_CONTROL_REGISTER |
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| 82 | |
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| 83 | ; Calculate bytes for first page |
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| 84 | mov ax, di |
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| 85 | neg ax ; AX = Max BYTEs for first page |
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| 86 | %ifdef USE_186 |
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| 87 | shl cx, 9 ; CX = Block size in BYTEs |
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| 88 | %else |
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| 89 | xchg cl, ch |
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| 90 | shl cx, 1 |
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| 91 | %endif |
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[545] | 92 | cmp cx, ax ; if we won't cross a physical page boundary... |
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| 93 | jbe SHORT .TransferLastDmaPageWithSizeInCX ; ...perform the transfer in one operation |
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[480] | 94 | |
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[545] | 95 | ; Calculate how much we can transfer on first and second rounds |
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[480] | 96 | xchg cx, ax ; CX = BYTEs for first page |
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| 97 | sub ax, cx ; AX = BYTEs for second page |
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[545] | 98 | push ax ; Save bytes for second transfer on stack |
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[480] | 99 | |
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| 100 | ; Transfer first DMA page |
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| 101 | call StartDMAtransferForXTCFwithDmaModeInBL |
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| 102 | pop cx ; Pop size for second DMA page |
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| 103 | |
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| 104 | .TransferLastDmaPageWithSizeInCX: |
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| 105 | ; Fall to StartDMAtransferForXTCFwithDmaModeInBL |
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| 106 | |
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| 107 | |
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| 108 | ;-------------------------------------------------------------------- |
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| 109 | ; StartDMAtransferForXTCFwithDmaModeInBL |
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[545] | 110 | ; Updated for XT-CFv3, 11-Apr-13 |
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[480] | 111 | ; Parameters: |
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[482] | 112 | ; BL: Byte for DMA Mode Register |
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[545] | 113 | ; CX: Number of BYTEs to transfer (512...32768 since max block size is limited to 64) |
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| 114 | ; DX: XT-CFv3 Control Register |
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| 115 | ; ES: Bits 3..0 have physical address bits 19..16 |
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| 116 | ; DI: Physical address bits 15..0 |
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[480] | 117 | ; Returns: |
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[545] | 118 | ; ES:DI updated (CX is added) |
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[480] | 119 | ; Corrupts registers: |
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| 120 | ; AX |
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| 121 | ;-------------------------------------------------------------------- |
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| 122 | ALIGN JUMP_ALIGN |
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| 123 | StartDMAtransferForXTCFwithDmaModeInBL: |
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| 124 | ; Program 8-bit DMA Controller |
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| 125 | ; Disable Interrupts and DMA Channel 3 during DMA setup |
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| 126 | mov al, SET_CH3_MASK_BIT |
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[545] | 127 | cli ; Disable interrupts - programming must be atomic |
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| 128 | out MASK_REGISTER_DMA8_out, al ; Disable DMA Channel 3 |
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[480] | 129 | |
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| 130 | ; Set DMA Mode (read or write using channel 3) |
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| 131 | mov al, bl |
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| 132 | out MODE_REGISTER_DMA8_out, al |
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| 133 | |
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[545] | 134 | ; Send start address to DMA controller |
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[480] | 135 | mov ax, es |
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| 136 | out PAGE_DMA8_CH_3, al |
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| 137 | mov ax, di |
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[545] | 138 | out CLEAR_FLIPFLOP_DMA8_out, al ; Reset flip-flop to low byte |
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[480] | 139 | out BASE_AND_CURRENT_ADDRESS_REGISTER_DMA8_CH3_out, al ; Low byte |
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| 140 | mov al, ah |
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| 141 | out BASE_AND_CURRENT_ADDRESS_REGISTER_DMA8_CH3_out, al ; High byte |
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| 142 | |
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| 143 | ; Set number of bytes to transfer (DMA controller must be programmed number of bytes - 1) |
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| 144 | mov ax, cx |
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[545] | 145 | dec ax ; DMA controller is programmed for one byte less |
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[480] | 146 | out BASE_AND_CURRENT_COUNT_REGISTER_DMA8_CH3_out, al ; Low byte |
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| 147 | mov al, ah |
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| 148 | out BASE_AND_CURRENT_COUNT_REGISTER_DMA8_CH3_out, al ; High byte |
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| 149 | |
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| 150 | ; Enable DMA Channel 3 |
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| 151 | mov al, CLEAR_CH3_MASK_BIT |
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[545] | 152 | out MASK_REGISTER_DMA8_out, al ; Enable DMA Channel 3 |
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| 153 | sti ; Enable interrupts |
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[480] | 154 | |
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[545] | 155 | ; XT-CF transfers 16 bytes at a time. We need to manually start transfer for every block by writing (anything) |
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| 156 | ; to the XT-CFv3 Control Register, which raises DRQ thereby passing system control to the 8237 DMA controller. |
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| 157 | ; The XT-CFv3 logic releases DRQ after 16 transfers, thereby handing control back to the CPU and allowing any other IRQs or |
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| 158 | ; DRQs to be serviced (which, on the PC and PC/XT will include DRAM refresh via DMA channel 0). The 16-byte transfers can |
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| 159 | ; also be interrupted by the DMA controller raising TC (i.e. when done). Each transfer cannot be otherwise interrupted |
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| 160 | ; and is therefore atomic (and hence fast). |
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[480] | 161 | |
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[545] | 162 | %if 0 ; Slow DMA code - works by checking 8237 status register after each 16-byte transfer, until it reports TC has been raised. |
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| 163 | ;ALIGN JUMP_ALIGN |
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| 164 | ;.TransferNextBlock: |
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| 165 | ; cli ; We want no ISR to read DMA Status Register before we do |
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| 166 | ; out dx, al ; Transfer up to 16 bytes to/from XT-CF card |
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| 167 | ; in al, STATUS_REGISTER_DMA8_in |
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| 168 | ; sti |
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| 169 | ; test al, FLG_CH3_HAS_REACHED_TERMINAL_COUNT |
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| 170 | ; jz SHORT .TransferNextBlock ; All bytes transferred? |
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[486] | 171 | %endif ; Slow DMA code |
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[480] | 172 | |
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[545] | 173 | %if 1 ; Fast DMA code - perform computed number of transfers, then check DMA status register to be sure |
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| 174 | push cx ; need byte count to update pointer at the end |
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| 175 | add cx, BYTE 15 ; We'll divide transfers in 16-byte atomic transfers, |
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| 176 | eSHR_IM cx, 4 ; so include any partial block, which will be terminated |
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| 177 | ALIGN JUMP_ALIGN ; by the DMA controller raising T/C |
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[486] | 178 | .TransferNextDmaBlock: |
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[545] | 179 | out dx, al ; Transfer up to 16 bytes to/from XT-CF card |
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| 180 | loop .TransferNextDmaBlock ; dec CX and loop if CX > 0, also adds required wait-state |
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[486] | 181 | inc cx ; set up CX, in case we need to do an extra iteration |
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[545] | 182 | in al, STATUS_REGISTER_DMA8_in ; check 8237 DMA controller status flags... |
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| 183 | test al, FLG_CH3_HAS_REACHED_TERMINAL_COUNT ; ... for channel 3 terminal count |
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| 184 | jz SHORT .TransferNextDmaBlock ; If not set, get more bytes |
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| 185 | pop cx ; get back requested bytes |
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[486] | 186 | %endif ; Fast DMA code |
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| 187 | |
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[545] | 188 | ; Update physical address in ES:DI - since IO might need several calls through this function either from here |
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| 189 | ; if crossing a physical page boundary, and from IdeTransfer.asm if requested sectors was > PIOVARS.wSectorsInBlock |
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| 190 | mov ax, es ; copy physical page address to ax |
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| 191 | add di, cx ; add requested bytes to di |
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| 192 | adc al, 0 ; and increment physical page address, if required |
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| 193 | mov es, ax ; and save it back in es |
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[486] | 194 | |
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[480] | 195 | ret |
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