source: xtideuniversalbios/trunk/XTIDE_Universal_BIOS/Src/Device/IDE/IdeCommand.asm@ 588

Last change on this file since 588 was 584, checked in by Tomi Tilli, 9 years ago

Changes to XTIDE Universal BIOS:

  • Added support for Lo-tech 8-bit IDE Adapter (untested)
File size: 8.8 KB
RevLine 
[150]1; Project name : XTIDE Universal BIOS
2; Description : IDE Device Command functions.
3
[376]4;
[445]5; XTIDE Universal BIOS and Associated Tools
[526]6; Copyright (C) 2009-2010 by Tomi Tilli, 2011-2013 by XTIDE Universal BIOS Team.
[376]7;
8; This program is free software; you can redistribute it and/or modify
9; it under the terms of the GNU General Public License as published by
10; the Free Software Foundation; either version 2 of the License, or
11; (at your option) any later version.
[445]12;
[376]13; This program is distributed in the hope that it will be useful,
14; but WITHOUT ANY WARRANTY; without even the implied warranty of
15; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16; GNU General Public License for more details.
[445]17; Visit http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
18;
[376]19
[150]20; Section containing code
21SECTION .text
22
23;--------------------------------------------------------------------
[507]24; IdeCommand_ResetMasterAndSlaveController
25; Parameters:
26; DS:DI: Ptr to DPT (in RAMVARS segment)
27; Returns:
28; AH: INT 13h Error Code
29; CF: Cleared if success, Set if error
30; Corrupts registers:
31; AL, BX, CX, DX
32;--------------------------------------------------------------------
33IdeCommand_ResetMasterAndSlaveController:
34 ; HSR0: Set_SRST
35 call AccessDPT_GetDeviceControlByteToAL
36 or al, FLG_DEVCONTROL_SRST | FLG_DEVCONTROL_nIEN ; Set Reset bit
37 OUTPUT_AL_TO_IDE_CONTROL_BLOCK_REGISTER DEVICE_CONTROL_REGISTER_out
38 mov ax, HSR0_RESET_WAIT_US
39 call Timer_DelayMicrosecondsFromAX
40
41 ; HSR1: Clear_wait
42 call AccessDPT_GetDeviceControlByteToAL
43 or al, FLG_DEVCONTROL_nIEN
44 and al, ~FLG_DEVCONTROL_SRST ; Clear reset bit
45 OUTPUT_AL_TO_IDE_CONTROL_BLOCK_REGISTER DEVICE_CONTROL_REGISTER_out
46 mov ax, HSR1_RESET_WAIT_US
47 call Timer_DelayMicrosecondsFromAX
48
49 ; HSR2: Check_status
50 mov bx, TIMEOUT_AND_STATUS_TO_WAIT(TIMEOUT_MAXIMUM, FLG_STATUS_BSY)
51 jmp IdeWait_PollStatusFlagInBLwithTimeoutInBH
52
53
54;--------------------------------------------------------------------
[150]55; IdeCommand_IdentifyDeviceToBufferInESSIwithDriveSelectByteInBH
56; Parameters:
57; BH: Drive Select byte for Drive and Head Select Register
[473]58; DX: Autodetected port for XT-CF
[150]59; DS: Segment to RAMVARS
60; ES:SI: Ptr to buffer to receive 512-byte IDE Information
61; CS:BP: Ptr to IDEVARS
62; Returns:
63; AH: INT 13h Error Code
64; CF: Cleared if success, Set if error
65; Corrupts registers:
[443]66; AL, BX, CX, DX, SI, DI, ES
[150]67;--------------------------------------------------------------------
[400]68IdeCommand_IdentifyDeviceToBufferInESSIwithDriveSelectByteInBH:
[150]69 ; Create fake DPT to be able to use Device.asm functions
70 call FindDPT_ForNewDriveToDSDI
[158]71 eMOVZX ax, bh
[150]72 mov [di+DPT.wFlags], ax
[473]73 call CreateDPT_StoreIdevarsOffsetAndBasePortFromCSBPtoDPTinDSDI
74 call IdeDPT_StoreDeviceTypeToDPTinDSDIfromIdevarsInCSBP
[365]75 mov BYTE [di+DPT_ATA.bBlockSize], 1 ; Block = 1 sector
[150]76
[443]77 ; Wait until drive motors have reached full speed
[473]78 cmp bp, BYTE ROMVARS.ideVars0 ; First controller?
[150]79 jne SHORT .SkipLongWaitSinceDriveIsNotPrimaryMaster
[473]80 test bh, FLG_DRVNHEAD_DRV ; Wait already done for Master
[150]81 jnz SHORT .SkipLongWaitSinceDriveIsNotPrimaryMaster
[545]82 mov bx, TIMEOUT_AND_STATUS_TO_WAIT(TIMEOUT_MOTOR_STARTUP, FLG_STATUS_BSY)
[507]83 call IdeWait_PollStatusFlagInBLwithTimeoutInBH
[150]84.SkipLongWaitSinceDriveIsNotPrimaryMaster:
85
86 ; Create IDEPACK without INTPACK
87 push bp
88 call Idepack_FakeToSSBP
89
[545]90%ifdef MODULE_8BIT_IDE
[480]91 push si
[584]92
93 ; Enable 8-bit PIO for DEVICE_8BIT_ATA (no need to verify device type here)
[480]94 call AH9h_Enable8bitModeForDevice8bitAta
[584]95
96 ; Set XT-CF mode. No need to check here if device is XT-CF or not.
[545]97%ifdef MODULE_8BIT_IDE_ADVANCED
[584]98 call AH1Eh_GetCurrentXTCFmodeToAX ; Reads from DPT_ATA.bDevice that we just stored
99 call AH9h_SetModeFromALtoXTCF ; Enables/disables 8-bit mode when necessary
[545]100%endif ; MODULE_8BIT_IDE_ADVANCED
[443]101 pop si
[545]102%endif ; MODULE_8BIT_IDE
[437]103
[150]104 ; Prepare to output Identify Device command
105 mov dl, 1 ; Sector count (required by IdeTransfer.asm)
106 mov al, COMMAND_IDENTIFY_DEVICE
[411]107 mov bx, TIMEOUT_AND_STATUS_TO_WAIT(TIMEOUT_DRQ, FLG_STATUS_DRQ)
[150]108 call Idepack_StoreNonExtParametersAndIssueCommandFromAL
109
110 ; Clean stack and return
[443]111 lea sp, [bp+SIZE_OF_IDEPACK_WITHOUT_INTPACK] ; This assumes BP hasn't changed between Idepack_FakeToSSBP and here
[150]112 pop bp
113 ret
114
115
116;--------------------------------------------------------------------
117; IdeCommand_OutputWithParameters
118; Parameters:
119; BH: System timer ticks for timeout
120; BL: IDE Status Register bit to poll after command
121; ES:SI: Ptr to buffer (for data transfer commands)
122; DS:DI: Ptr to DPT (in RAMVARS segment)
123; SS:BP: Ptr to IDEPACK
124; Returns:
125; AH: INT 13h Error Code
[249]126; CX: Number of successfully transferred sectors (for transfer commands)
[150]127; CF: Cleared if success, Set if error
128; Corrupts registers:
[249]129; AL, BX, (CX), DX, (ES:SI for data transfer commands)
[150]130;--------------------------------------------------------------------
131ALIGN JUMP_ALIGN
[400]132IdeCommand_OutputWithParameters:
[158]133 push bx ; Store status register bits to poll
[150]134
135 ; Select Master or Slave drive and output head number or LBA28 top bits
[400]136 call IdeCommand_SelectDrive
[150]137 jc SHORT .DriveNotReady
138
139 ; Output Device Control Byte to enable or disable interrupts
140 mov al, [bp+IDEPACK.bDeviceControl]
[400]141%ifdef MODULE_IRQ
[158]142 test al, FLG_DEVCONTROL_nIEN ; Interrupts disabled?
[152]143 jnz SHORT .DoNotSetInterruptInServiceFlag
[158]144
145 ; Clear Task Flag and set Interrupt In-Service Flag
[152]146 push ds
[540]147 LOAD_BDA_SEGMENT_TO ds, dx
148 mov BYTE [BDA.bHDTaskFlg], 1 ; Will be adjusted to zero later
[152]149 pop ds
150.DoNotSetInterruptInServiceFlag:
[266]151%endif
[267]152 OUTPUT_AL_TO_IDE_CONTROL_BLOCK_REGISTER DEVICE_CONTROL_REGISTER_out
[150]153
154 ; Output Feature Number
155 mov al, [bp+IDEPACK.bFeatures]
[267]156 OUTPUT_AL_TO_IDE_REGISTER FEATURES_REGISTER_out
[150]157
158 ; Output Sector Address High (only used by LBA48)
[285]159%ifdef MODULE_EBIOS
[294]160 eMOVZX ax, [bp+IDEPACK.bLbaLowExt] ; Zero sector count
[150]161 mov cx, [bp+IDEPACK.wLbaMiddleAndHighExt]
[400]162 call OutputSectorCountAndAddress
[285]163%endif
[150]164
165 ; Output Sector Address Low
166 mov ax, [bp+IDEPACK.wSectorCountAndLbaLow]
167 mov cx, [bp+IDEPACK.wLbaMiddleAndHigh]
[400]168 call OutputSectorCountAndAddress
[150]169
170 ; Output command
171 mov al, [bp+IDEPACK.bCommand]
[267]172 OUTPUT_AL_TO_IDE_REGISTER COMMAND_REGISTER_out
[150]173
174 ; Wait until command completed
[400]175 pop bx ; Pop status and timeout for polling
176 cmp bl, FLG_STATUS_DRQ ; Data transfer started?
177 jne SHORT .WaitUntilNonTransferCommandCompletes
[493]178%ifdef MODULE_8BIT_IDE_ADVANCED
[545]179 cmp BYTE [di+DPT_ATA.bDevice], DEVICE_8BIT_JRIDE_ISA
180 jae SHORT JrIdeTransfer_StartWithCommandInAL ; DEVICE_8BIT_JRIDE_ISA or DEVICE_8BIT_ADP50L
[480]181%endif
[474]182 jmp IdeTransfer_StartWithCommandInAL
[400]183
184.WaitUntilNonTransferCommandCompletes:
185%ifdef MODULE_IRQ
[150]186 test BYTE [bp+IDEPACK.bDeviceControl], FLG_DEVCONTROL_nIEN
[400]187 jz SHORT .PollStatusFlagInsteadOfWaitIrq
188 jmp IdeWait_IRQorStatusFlagInBLwithTimeoutInBH
189.PollStatusFlagInsteadOfWaitIrq:
190%endif
191 jmp IdeWait_PollStatusFlagInBLwithTimeoutInBH
[150]192
193.DriveNotReady:
194 pop bx ; Clean stack
195 ret
196
197
198;--------------------------------------------------------------------
199; IdeCommand_SelectDrive
200; Parameters:
201; DS:DI: Ptr to DPT (in RAMVARS segment)
202; SS:BP: Ptr to IDEPACK
203; Returns:
204; AH: INT 13h Error Code
205; CF: Cleared if success, Set if error
206; Corrupts registers:
207; AL, BX, CX, DX
208;--------------------------------------------------------------------
209ALIGN JUMP_ALIGN
[400]210IdeCommand_SelectDrive:
[444]211 ; We use different timeout value when detecting drives.
212 ; This prevents unnecessary long delays when drive is not present.
[473]213 mov cx, TIMEOUT_AND_STATUS_TO_WAIT(TIMEOUT_DRDY, FLG_STATUS_DRDY)
[444]214 cmp WORD [RAMVARS.wDrvDetectSignature], RAMVARS_DRV_DETECT_SIGNATURE
[473]215 eCMOVE ch, TIMEOUT_SELECT_DRIVE_DURING_DRIVE_DETECTION
[408]216
[150]217 ; Select Master or Slave Drive
218 mov al, [bp+IDEPACK.bDrvAndHead]
[267]219 OUTPUT_AL_TO_IDE_REGISTER DRIVE_AND_HEAD_SELECT_REGISTER
[473]220 mov bx, cx
[400]221 call IdeWait_PollStatusFlagInBLwithTimeoutInBH
[150]222
[281]223 ; Ignore errors from IDE Error Register (set by previous command)
[285]224 cmp ah, RET_HD_TIMEOUT
225 je SHORT .FailedToSelectDrive
226 xor ax, ax ; Always success unless timeout
227 ret
228.FailedToSelectDrive:
[281]229 stc
[279]230 ret
[150]231
[279]232
[150]233;--------------------------------------------------------------------
234; OutputSectorCountAndAddress
235; Parameters:
236; AH: LBA low bits (Sector Number)
237; AL: Sector Count
238; CL: LBA middle bits (Cylinder Number low)
239; CH: LBA high bits (Cylinder Number high)
240; DS:DI: Ptr to DPT (in RAMVARS segment)
241; Returns:
242; Nothing
243; Corrupts registers:
244; AL, BX, DX
245;--------------------------------------------------------------------
246ALIGN JUMP_ALIGN
[400]247OutputSectorCountAndAddress:
[267]248 OUTPUT_AL_TO_IDE_REGISTER SECTOR_COUNT_REGISTER
[150]249
250 mov al, ah
[267]251 OUTPUT_AL_TO_IDE_REGISTER LBA_LOW_REGISTER
[150]252
253 mov al, cl
[267]254 OUTPUT_AL_TO_IDE_REGISTER LBA_MIDDLE_REGISTER
[150]255
256 mov al, ch
[473]257 OUTPUT_AL_TO_IDE_REGISTER LBA_HIGH_REGISTER
258 ret
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