source: xtideuniversalbios/trunk/XTIDE_Universal_BIOS/Inc/RomVars.inc@ 580

Last change on this file since 580 was 567, checked in by krille_n_@…, 10 years ago

Changes:

  • Renamed MODULE_FEATURE_SETS to MODULE_POWER_MANAGEMENT.
  • Renamed MODULE_VERY_LATE_INITIALIZATION to MODULE_VERY_LATE_INIT and removed it from the official builds.
  • Removed the code that skips detection of slave drives on XT-CF controllers since slave drives can be used with Lo-tech ISA CompactFlash boards.
  • Added autodetection of the SVC ADP50L controller to XTIDECFG.
  • The autodetection of XT-CF controllers now requires MODULE_8BIT_IDE_ADVANCED in the loaded BIOS.
  • Fixed a bug in XTIDECFG from r502 where the "Base (cmd block) address" menu option would be displayed when a serial device was selected as the IDE controller.
  • XTIDECFG would display the "Enable interrupt" menu option for the XTIDE r1 but not for the XTIDE r2. It's now displayed for both controller types.
  • Disabled the "Internal Write Cache" menu option in the Master/Slave Drive menus for serial device type drives.
  • Optimizations and other fixes.
File size: 8.5 KB
Line 
1; Project name : XTIDE Universal BIOS
2; Description : Defines for ROMVARS struct containing variables stored
3; in BIOS ROM.
4
5;
6; XTIDE Universal BIOS and Associated Tools
7; Copyright (C) 2009-2010 by Tomi Tilli, 2011-2013 by XTIDE Universal BIOS Team.
8;
9; This program is free software; you can redistribute it and/or modify
10; it under the terms of the GNU General Public License as published by
11; the Free Software Foundation; either version 2 of the License, or
12; (at your option) any later version.
13;
14; This program is distributed in the hope that it will be useful,
15; but WITHOUT ANY WARRANTY; without even the implied warranty of
16; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17; GNU General Public License for more details.
18; Visit http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
19;
20
21%ifndef ROMVARS_INC
22%define ROMVARS_INC
23
24; ROM Variables. Written to the ROM image before flashing.
25struc ROMVARS
26 .wRomSign resb 2 ; ROM Signature (AA55h)
27 .bRomSize resb 1 ; ROM size in 512 byte blocks
28 .rgbJump resb 3 ; First instruction to ROM init (jmp)
29
30 .rgbSign resb 8 ; Signature for XTIDE Configurator Program
31 .szTitle resb 31 ; BIOS title string
32 .szVersion resb 25 ; BIOS version string
33
34 .wFlags resb 2 ; Word for ROM flags
35 .wDisplayMode resb 2 ; Display mode for boot menu
36 .wBootTimeout resb 2 ; Boot Menu selection timeout in system timer ticks
37 .bIdeCnt resb 1 ; Number of available IDE controllers
38 .bBootDrv resb 1 ; Default drive to boot from
39 .bMinFddCnt resb 1 ; Minimum number of Floppy Drives
40 .bStealSize resb 1 ; Number of 1kB blocks stolen from 640kB base RAM
41 .bIdleTimeout resb 1 ; Standby timer value
42
43 .ideVarsBegin:
44 .ideVars0 resb IDEVARS_size
45 .ideVars1 resb IDEVARS_size
46 .ideVars2 resb IDEVARS_size
47 .ideVars3 resb IDEVARS_size
48
49%ifdef MODULE_SERIAL
50 .ideVarsSerialAuto resb IDEVARS_size
51%endif
52
53 .ideVarsEnd:
54endstruc
55
56%ifndef CHECK_FOR_UNUSED_ENTRYPOINTS
57 %if ROMVARS.ideVarsEnd & 0xff00 <> 0
58 %error ".ideVars structures must fit within the first 256 bytes of the ROM image"
59 %endif
60 %if (ROMVARS.ideVarsEnd - ROMVARS.ideVarsBegin) = 0
61 %error "there must be at least one .ideVars structure, it would be bizarre if this were not true, but it is assumed in the ah0h reset code."
62 %endif
63%endif
64
65NUMBER_OF_IDEVARS EQU ((ROMVARS.ideVarsEnd - ROMVARS.ideVarsBegin) / IDEVARS_size)
66
67; Bit defines for ROMVARS.wFlags
68FLG_ROMVARS_FULLMODE EQU (1<<0) ; Full operating mode (steals base RAM, supports EBIOS etc.)
69FLG_ROMVARS_SERIAL_SCANDETECT EQU (1<<3) ; Scan COM ports at the end of drive detection. Can also be invoked
70 ; by holding down the ALT key at the end of drive detection.
71 ; (Conveniently, this is 8, a fact we exploit when testing the bit)
72
73; Here in case the configuration needs to know functionality is present
74FLG_ROMVARS_MODULE_POWER_MANAGEMENT EQU (1<<5)
75FLG_ROMVARS_MODULE_8BIT_IDE EQU (1<<6)
76FLG_ROMVARS_MODULE_8BIT_IDE_ADVANCED EQU (1<<7)
77FLG_ROMVARS_MODULE_ADVANCED_ATA EQU (1<<8)
78FLG_ROMVARS_MODULE_BOOT_MENU EQU (1<<9)
79FLG_ROMVARS_MODULE_EBIOS EQU (1<<10)
80FLG_ROMVARS_MODULE_HOTKEYS EQU (1<<11)
81FLG_ROMVARS_MODULE_IRQ EQU (1<<12)
82FLG_ROMVARS_MODULE_SERIAL EQU (1<<13)
83FLG_ROMVARS_MODULE_SERIAL_FLOPPY EQU (1<<14)
84FLG_ROMVARS_MODULE_STRINGS_COMPRESSED EQU (1<<15)
85
86
87; Boot Menu Display Modes (see Assembly Library Display.inc for standard modes)
88DEFAULT_TEXT_MODE EQU 4
89
90
91; Controller specific variables
92struc IDEVARS
93;;; Word 0
94 .wSerialPortAndBaud: ; Serial connection port (low, divided by 4) and baud rate divisor (high)
95 .wBasePort: ; IDE Base Port for Command Block (usual) Registers
96 .bSerialPort resb 1
97 .bSerialBaud resb 1
98
99;;; Word 1
100 .wControlBlockPort:
101 .bSerialUnused resb 1 ; IDE Base Port for Control Block Registers
102
103 .wSerialCOMPortCharAndDevice: ; In DetectPrint, we grab the COM Port char and Device at the same time
104 .bSerialCOMPortChar resb 1 ; Serial connection COM port number/letter
105
106;;; Word 2
107 .bDevice resb 1 ; Device type
108 .bIRQ resb 1 ; Interrupt Request Number
109
110;;; And more...
111 .drvParamsMaster resb DRVPARAMS_size
112 .drvParamsSlave resb DRVPARAMS_size
113endstruc
114
115%ifndef CHECK_FOR_UNUSED_ENTRYPOINTS
116 %if IDEVARS.bSerialCOMPortChar+1 != IDEVARS.bDevice
117 %error "IDEVARS.bSerialCOMPortChar needs to come immediately before IDEVARS.bDevice so that both bytes can be fetched at the same time inside DetectPrint.asm"
118 %endif
119%endif
120
121STANDARD_CONTROL_BLOCK_OFFSET EQU 200h
122XTIDE_CONTROL_BLOCK_OFFSET EQU 8h ; for XTIDE, A3 is used to control selected register (CS0 vs CS1)...
123XTCF_CONTROL_BLOCK_OFFSET EQU 10h ; ...and for XT-CF (all variants), it's A4
124ADP50L_CONTROL_BLOCK_OFFSET EQU 10h
125
126; Default values for Port and PortCtrl, shared with the configurator
127;
128DEVICE_XTIDE_DEFAULT_PORT EQU 300h ; Also the default port for XT-CF
129DEVICE_XTIDE_DEFAULT_PORTCTRL EQU (DEVICE_XTIDE_DEFAULT_PORT + XTIDE_CONTROL_BLOCK_OFFSET)
130; Note XT-CF control port is SHL 1 relative to XTIDE, and coded that way hence no need for specific definition like...
131; DEVICE_XTCF_DEFAULT_PORTCTRL EQU (DEVICE_XTIDE_DEFAULT_PORT + XTCF_CONTROL_BLOCK_OFFSET)
132
133DEVICE_ATA_PRIMARY_PORT EQU 1F0h
134DEVICE_ATA_PRIMARY_PORTCTRL EQU (DEVICE_ATA_PRIMARY_PORT + STANDARD_CONTROL_BLOCK_OFFSET)
135
136DEVICE_ATA_SECONDARY_PORT EQU 170h
137DEVICE_ATA_SECONDARY_PORTCTRL EQU (DEVICE_ATA_SECONDARY_PORT + STANDARD_CONTROL_BLOCK_OFFSET)
138
139DEVICE_ATA_TERTIARY_PORT EQU 1E8h
140DEVICE_ATA_TERTIARY_PORTCTRL EQU (DEVICE_ATA_TERTIARY_PORT + STANDARD_CONTROL_BLOCK_OFFSET)
141
142DEVICE_ATA_QUATERNARY_PORT EQU 168h
143DEVICE_ATA_QUATERNARY_PORTCTRL EQU (DEVICE_ATA_QUATERNARY_PORT + STANDARD_CONTROL_BLOCK_OFFSET)
144
145
146; Device types for IDEVARS.bDevice
147; IDE Devices are grouped so device numbers cannot be changed without modifying code elsewhere!
148;
149COUNT_OF_STANDARD_IDE_DEVICES EQU 2 ; 16- and 32-bit controllers
150COUNT_OF_8BIT_IDE_DEVICES EQU 8
151COUNT_OF_ALL_IDE_DEVICES EQU (COUNT_OF_8BIT_IDE_DEVICES + COUNT_OF_STANDARD_IDE_DEVICES)
152; Standard port mapped I/O
153DEVICE_16BIT_ATA EQU (0<<1)
154DEVICE_32BIT_ATA EQU (1<<1)
155DEVICE_8BIT_ATA EQU ((COUNT_OF_STANDARD_IDE_DEVICES+0)<<1) ; 16- or 32-bit controller in 8-bit mode
156DEVICE_8BIT_XTIDE_REV1 EQU ((COUNT_OF_STANDARD_IDE_DEVICES+1)<<1)
157; Address lines A0 and A3 are swapped
158DEVICE_8BIT_XTIDE_REV2 EQU ((COUNT_OF_STANDARD_IDE_DEVICES+2)<<1) ; Or rev 1 with swapped A0 and A3
159; IDE Register offsets are SHL 1
160DEVICE_8BIT_XTCF_PIO8 EQU ((COUNT_OF_STANDARD_IDE_DEVICES+3)<<1) ; XT-CF using 8-bit PIO mode
161DEVICE_8BIT_XTCF_PIO8_WITH_BIU_OFFLOAD EQU ((COUNT_OF_STANDARD_IDE_DEVICES+4)<<1) ; XT-CF using 8-bit PIO mode, but with 16-bit instructions
162DEVICE_8BIT_XTCF_DMA EQU ((COUNT_OF_STANDARD_IDE_DEVICES+5)<<1) ; XT-CFv3 using DMA
163; Memory Mapped I/O
164DEVICE_8BIT_JRIDE_ISA EQU ((COUNT_OF_STANDARD_IDE_DEVICES+6)<<1) ; JR-IDE/ISA (Memory Mapped I/O)
165DEVICE_8BIT_ADP50L EQU ((COUNT_OF_STANDARD_IDE_DEVICES+7)<<1) ; SVC ADP50L (Memory Mapped I/O)
166; Virtual devices
167DEVICE_SERIAL_PORT EQU (COUNT_OF_ALL_IDE_DEVICES<<1)
168
169
170
171; Master/Slave drive specific parameters
172struc DRVPARAMS
173 .wFlags resb 2 ; Drive flags
174 .dwMaximumLBA: ; User specified maximum number of sectors
175 .wCylinders resb 2 ; User specified cylinders (1...16383)
176 .wHeadsAndSectors:
177 .bHeads resb 1 ; User specified Heads (1...16)
178 .bSect resb 1 ; User specified Sectors per track (1...63)
179endstruc
180
181; Bit defines for DRVPARAMS.wFlags
182MASK_DRVPARAMS_WRITECACHE EQU (3<<0) ; Bits 0...1, Drive internal write cache settings (must start at bit 0)
183 DEFAULT_WRITE_CACHE EQU 0 ; Must be 0
184 DISABLE_WRITE_CACHE EQU 1
185 ENABLE_WRITE_CACHE EQU 2
186MASK_DRVPARAMS_TRANSLATEMODE EQU (3<<TRANSLATEMODE_FIELD_POSITION) ; Bits 2...3, Position shared with DPT
187 TRANSLATEMODE_FIELD_POSITION EQU 2
188 TRANSLATEMODE_NORMAL EQU 0 ; Must be zero
189 TRANSLATEMODE_LARGE EQU 1
190 TRANSLATEMODE_ASSISTED_LBA EQU 2 ; 28-bit or 48-bit LBA
191 TRANSLATEMODE_AUTO EQU 3 ; Only available in ROMVARS, not in DPTs
192FLG_DRVPARAMS_BLOCKMODE EQU (1<<4) ; Enable Block mode transfers
193FLG_DRVPARAMS_USERCHS EQU (1<<5) ; User specified P-CHS values
194 MAX_PCHS_CYLINDERS EQU 16383
195 MAX_PCHS_HEADS EQU 16
196 MAX_PCHS_SECTORS_PER_TRACK EQU 63
197 MAX_PCHS_TOTAL_SECTOR_COUNT EQU (MAX_PCHS_CYLINDERS * MAX_PCHS_HEADS * MAX_PCHS_SECTORS_PER_TRACK) ; 16,514,064
198FLG_DRVPARAMS_USERLBA EQU (1<<6) ; User specified LBA value
199
200%endif ; ROMVARS_INC
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