| 1 | ; Project name : XTIDE Universal BIOS
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| 2 | ; Description : Defines for ROMVARS struct containing variables stored
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| 3 | ; in BIOS ROM.
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| 4 | %ifndef ROMVARS_INC
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| 5 | %define ROMVARS_INC
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| 6 |
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| 7 | ; ROM Variables. There are written to ROM image before flashing.
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| 8 | struc ROMVARS
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| 9 | .wRomSign resb 2 ; ROM Signature (AA55h)
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| 10 | .bRomSize resb 1 ; ROM size in 512 byte blocks
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| 11 | .rgbJump resb 3 ; First instruction to ROM init (jmp)
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| 12 |
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| 13 | .rgbSign resb 8 ; Signature for XTIDE Configurator Program
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| 14 | .szTitle resb 31 ; BIOS title string
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| 15 | .szVersion resb 25 ; BIOS version string
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| 16 |
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| 17 | .wFlags resb 2 ; Word for ROM flags
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| 18 | .wBootTimeout resb 2 ; Boot Menu selection timeout in system timer ticks
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| 19 | .bIdeCnt resb 1 ; Number of available IDE controllers
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| 20 | .bBootDrv resb 1 ; Boot Menu default drive
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| 21 | .bMinFddCnt resb 1 ; Minimum number of Floppy Drives
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| 22 | .bStealSize resb 1 ; Number of 1kB blocks stolen from 640kB base RAM
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| 23 |
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| 24 | .ideVars0 resb IDEVARS_size
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| 25 | .ideVars1 resb IDEVARS_size
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| 26 | .ideVars2 resb IDEVARS_size
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| 27 | .ideVars3 resb IDEVARS_size
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| 28 | endstruc
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| 29 |
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| 30 | ; Bit defines for ROMVARS.wFlags
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| 31 | FLG_ROMVARS_FULLMODE EQU (1<<0) ; Full operating mode (steals base RAM, supports EBIOS etc.)
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| 32 | FLG_ROMVARS_DRVXLAT EQU (1<<2) ; Enable drive number translation
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| 33 |
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| 34 |
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| 35 | ; Controller specific variables
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| 36 | struc IDEVARS
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| 37 | .wPort resb 2 ; IDE Base Port for Command Block (usual) Registers
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| 38 | .wPortCtrl resb 2 ; IDE Base Port for Control Block Registers
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| 39 | .bBusType resb 1 ; Bus type
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| 40 | .bIRQ resb 1 ; Interrupt Request Number
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| 41 | .drvParamsMaster resb DRVPARAMS_size
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| 42 | .drvParamsSlave resb DRVPARAMS_size
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| 43 | endstruc
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| 44 |
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| 45 | ; Bus types for IDEVARS.bBusType
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| 46 | BUS_TYPE_8_DUAL EQU (0<<1) ; XTIDE transfers with two 8-bit data ports
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| 47 | BUS_TYPE_16 EQU (1<<1) ; Normal 16-bit AT-IDE transfers
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| 48 | BUS_TYPE_32 EQU (2<<1) ; 32-bit VLB and PCI transfers
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| 49 | BUS_TYPE_8_SINGLE EQU (3<<1) ; 8-bit transfers with single 8-bit data port
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| 50 |
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| 51 |
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| 52 | ; Master/Slave drive specific parameters
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| 53 | struc DRVPARAMS
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| 54 | .wFlags resb 2 ; Drive flags
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| 55 | .wCylinders resb 2 ; User specified cylinders (1...16383)
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| 56 | .wHeadsAndSectors:
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| 57 | .bHeads resb 1 ; User specified Heads (1...16)
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| 58 | .bSect resb 1 ; User specified Sectors per track (1...63)
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| 59 | endstruc
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| 60 |
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| 61 | ; Bit defines for DRVPARAMS.wFlags
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| 62 | FLG_DRVPARAMS_USERCHS EQU (1<<0) ; User specified P-CHS values
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| 63 | FLG_DRVPARAMS_BLOCKMODE EQU (1<<1) ; Enable Block mode transfers
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| 64 |
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| 65 |
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| 66 | %endif ; ROMVARS_INC
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