| 1 | ; Project name : XTIDE Universal BIOS
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| 2 | ; Description : Defines for ROMVARS struct containing variables stored
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| 3 | ; in BIOS ROM.
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| 4 |
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| 5 | ;
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| 6 | ; XTIDE Universal BIOS and Associated Tools
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| 7 | ; Copyright (C) 2009-2010 by Tomi Tilli, 2011-2013 by XTIDE Universal BIOS Team.
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| 8 | ;
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| 9 | ; This program is free software; you can redistribute it and/or modify
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| 10 | ; it under the terms of the GNU General Public License as published by
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| 11 | ; the Free Software Foundation; either version 2 of the License, or
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| 12 | ; (at your option) any later version.
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| 13 | ;
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| 14 | ; This program is distributed in the hope that it will be useful,
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| 15 | ; but WITHOUT ANY WARRANTY; without even the implied warranty of
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| 16 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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| 17 | ; GNU General Public License for more details.
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| 18 | ; Visit http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
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| 19 | ;
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| 20 |
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| 21 | %ifndef ROMVARS_INC
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| 22 | %define ROMVARS_INC
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| 23 |
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| 24 | ; ROM Variables. Written to the ROM image before flashing.
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| 25 | struc ROMVARS
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| 26 | .wRomSign resb 2 ; ROM Signature (AA55h)
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| 27 | .bRomSize resb 1 ; ROM size in 512 byte blocks
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| 28 | .rgbJump resb 3 ; First instruction to ROM init (jmp)
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| 29 |
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| 30 | .rgbSign resb 8 ; Signature for XTIDE Configurator Program
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| 31 | .szTitle resb 31 ; BIOS title string
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| 32 | .szVersion resb 25 ; BIOS version string
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| 33 |
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| 34 | .wFlags resb 2 ; Word for ROM flags
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| 35 | .wDisplayMode resb 2 ; Display mode for boot menu
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| 36 | .wBootTimeout resb 2 ; Boot Menu selection timeout in system timer ticks
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| 37 | .bIdeCnt resb 1 ; Number of available IDE controllers
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| 38 | .bBootDrv resb 1 ; Default drive to boot from
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| 39 | .bMinFddCnt resb 1 ; Minimum number of Floppy Drives
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| 40 | .bStealSize resb 1 ; Number of 1kB blocks stolen from 640kB base RAM
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| 41 | .bIdleTimeout resb 1 ; Standby timer value
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| 42 |
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| 43 | .ideVarsBegin:
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| 44 | .ideVars0 resb IDEVARS_size
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| 45 | .ideVars1 resb IDEVARS_size
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| 46 | .ideVars2 resb IDEVARS_size
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| 47 | .ideVars3 resb IDEVARS_size
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| 48 |
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| 49 | %ifdef MODULE_SERIAL
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| 50 | .ideVarsSerialAuto resb IDEVARS_size
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| 51 | %endif
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| 52 |
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| 53 | .ideVarsEnd:
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| 54 | endstruc
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| 55 |
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| 56 | %ifndef CHECK_FOR_UNUSED_ENTRYPOINTS
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| 57 | %if ROMVARS.ideVarsEnd & 0xff00 <> 0
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| 58 | %error ".ideVars structures must fit within the first 256 bytes of the ROM image"
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| 59 | %endif
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| 60 | %if (ROMVARS.ideVarsEnd - ROMVARS.ideVarsBegin) = 0
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| 61 | %error "there must be at least one .ideVars structure, it would be bizarre if this were not true, but it is assumed in the ah0h reset code."
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| 62 | %endif
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| 63 | %endif
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| 64 |
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| 65 | NUMBER_OF_IDEVARS EQU ((ROMVARS.ideVarsEnd - ROMVARS.ideVarsBegin) / IDEVARS_size)
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| 66 |
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| 67 | ; Bit defines for ROMVARS.wFlags
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| 68 | FLG_ROMVARS_FULLMODE EQU (1<<0) ; Full operating mode (steals base RAM, supports EBIOS etc.)
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| 69 | FLG_ROMVARS_SERIAL_SCANDETECT EQU (1<<3) ; Scan COM ports at the end of drive detection. Can also be invoked
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| 70 | ; by holding down the ALT key at the end of drive detection.
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| 71 | ; (Conveniently, this is 8, a fact we exploit when testing the bit)
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| 72 |
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| 73 | ; Here in case the configuration needs to know functionality is present
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| 74 | FLG_ROMVARS_MODULE_FEATURE_SETS EQU (1<<5)
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| 75 | FLG_ROMVARS_MODULE_8BIT_IDE EQU (1<<6)
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| 76 | FLG_ROMVARS_MODULE_8BIT_IDE_ADVANCED EQU (1<<7)
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| 77 | FLG_ROMVARS_MODULE_ADVANCED_ATA EQU (1<<8)
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| 78 | FLG_ROMVARS_MODULE_BOOT_MENU EQU (1<<9)
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| 79 | FLG_ROMVARS_MODULE_EBIOS EQU (1<<10)
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| 80 | FLG_ROMVARS_MODULE_HOTKEYS EQU (1<<11)
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| 81 | FLG_ROMVARS_MODULE_IRQ EQU (1<<12)
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| 82 | FLG_ROMVARS_MODULE_SERIAL EQU (1<<13)
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| 83 | FLG_ROMVARS_MODULE_SERIAL_FLOPPY EQU (1<<14)
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| 84 | FLG_ROMVARS_MODULE_STRINGS_COMPRESSED EQU (1<<15)
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| 85 |
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| 86 |
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| 87 | ; Boot Menu Display Modes (see Assembly Library Display.inc for standard modes)
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| 88 | DEFAULT_TEXT_MODE EQU 4
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| 89 |
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| 90 |
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| 91 | ; Controller specific variables
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| 92 | struc IDEVARS
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| 93 | ;;; Word 0
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| 94 | .wSerialPortAndBaud: ; Serial connection port (low, divided by 4) and baud rate divisor (high)
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| 95 | .wBasePort: ; IDE Base Port for Command Block (usual) Registers
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| 96 | .bSerialPort resb 1
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| 97 | .bSerialBaud resb 1
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| 98 |
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| 99 | ;;; Word 1
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| 100 | .wControlBlockPort:
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| 101 | .bSerialUnused resb 1 ; IDE Base Port for Control Block Registers
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| 102 |
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| 103 | .wSerialCOMPortCharAndDevice: ; In DetectPrint, we grab the COM Port char and Device at the same time
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| 104 | .bSerialCOMPortChar resb 1 ; Serial connection COM port number/letter
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| 105 |
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| 106 | ;;; Word 2
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| 107 | .bDevice resb 1 ; Device type
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| 108 | .bIRQ resb 1 ; Interrupt Request Number
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| 109 |
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| 110 | ;;; And more...
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| 111 | .drvParamsMaster resb DRVPARAMS_size
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| 112 | .drvParamsSlave resb DRVPARAMS_size
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| 113 | endstruc
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| 114 |
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| 115 | %ifndef CHECK_FOR_UNUSED_ENTRYPOINTS
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| 116 | %if IDEVARS.bSerialCOMPortChar+1 != IDEVARS.bDevice
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| 117 | %error "IDEVARS.bSerialCOMPortChar needs to come immediately before IDEVARS.bDevice so that both bytes can be fetched at the same time inside DetectPrint.asm"
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| 118 | %endif
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| 119 | %endif
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| 120 |
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| 121 | STANDARD_CONTROL_BLOCK_OFFSET EQU 200h
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| 122 | XTIDE_CONTROL_BLOCK_OFFSET EQU 8h ; for XTIDE, A3 is used to control selected register (CS0 vs CS1)...
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| 123 | XTCF_CONTROL_BLOCK_OFFSET EQU 10h ; ...and for XT-CF (all variants), it's A4
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| 124 | ADP50L_CONTROL_BLOCK_OFFSET EQU 10h
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| 125 |
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| 126 | ; Default values for Port and PortCtrl, shared with the configurator
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| 127 | ;
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| 128 | DEVICE_XTIDE_DEFAULT_PORT EQU 300h ; Also the default port for XT-CF
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| 129 | DEVICE_XTIDE_DEFAULT_PORTCTRL EQU (DEVICE_XTIDE_DEFAULT_PORT + XTIDE_CONTROL_BLOCK_OFFSET)
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| 130 | ; Note XT-CF control port is SHL 1 relative to XTIDE, and coded that way hence no need for specific definition like...
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| 131 | ; DEVICE_XTCF_DEFAULT_PORTCTRL EQU (DEVICE_XTIDE_DEFAULT_PORT + XTCF_CONTROL_BLOCK_OFFSET)
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| 132 |
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| 133 | DEVICE_ATA_PRIMARY_PORT EQU 1F0h
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| 134 | DEVICE_ATA_PRIMARY_PORTCTRL EQU (DEVICE_ATA_PRIMARY_PORT + STANDARD_CONTROL_BLOCK_OFFSET)
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| 135 |
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| 136 | DEVICE_ATA_SECONDARY_PORT EQU 170h
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| 137 | DEVICE_ATA_SECONDARY_PORTCTRL EQU (DEVICE_ATA_SECONDARY_PORT + STANDARD_CONTROL_BLOCK_OFFSET)
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| 138 |
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| 139 | DEVICE_ATA_TERTIARY_PORT EQU 1E8h
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| 140 | DEVICE_ATA_TERTIARY_PORTCTRL EQU (DEVICE_ATA_TERTIARY_PORT + STANDARD_CONTROL_BLOCK_OFFSET)
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| 141 |
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| 142 | DEVICE_ATA_QUATERNARY_PORT EQU 168h
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| 143 | DEVICE_ATA_QUATERNARY_PORTCTRL EQU (DEVICE_ATA_QUATERNARY_PORT + STANDARD_CONTROL_BLOCK_OFFSET)
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| 144 |
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| 145 |
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| 146 | ; Device types for IDEVARS.bDevice
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| 147 | ; IDE Devices are grouped so device numbers cannot be changed without modifying code elsewhere!
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| 148 | ;
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| 149 | COUNT_OF_STANDARD_IDE_DEVICES EQU 2 ; 16- and 32-bit controllers
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| 150 | COUNT_OF_8BIT_IDE_DEVICES EQU 8
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| 151 | COUNT_OF_ALL_IDE_DEVICES EQU (COUNT_OF_8BIT_IDE_DEVICES + COUNT_OF_STANDARD_IDE_DEVICES)
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| 152 | ; Standard port mapped I/O
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| 153 | DEVICE_16BIT_ATA EQU (0<<1)
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| 154 | DEVICE_32BIT_ATA EQU (1<<1)
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| 155 | DEVICE_8BIT_ATA EQU ((COUNT_OF_STANDARD_IDE_DEVICES+0)<<1) ; 16- or 32-bit controller in 8-bit mode
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| 156 | DEVICE_8BIT_XTIDE_REV1 EQU ((COUNT_OF_STANDARD_IDE_DEVICES+1)<<1)
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| 157 | ; Address lines A0 and A3 are swapped
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| 158 | DEVICE_8BIT_XTIDE_REV2 EQU ((COUNT_OF_STANDARD_IDE_DEVICES+2)<<1) ; Or rev 1 with swapped A0 and A3
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| 159 | ; IDE Register offsets are SHL 1
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| 160 | DEVICE_8BIT_XTCF_PIO8 EQU ((COUNT_OF_STANDARD_IDE_DEVICES+3)<<1) ; XT-CF using 8-bit PIO mode
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| 161 | DEVICE_8BIT_XTCF_PIO8_WITH_BIU_OFFLOAD EQU ((COUNT_OF_STANDARD_IDE_DEVICES+4)<<1) ; XT-CF using 8-bit PIO mode, but with 16-bit instructions
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| 162 | DEVICE_8BIT_XTCF_DMA EQU ((COUNT_OF_STANDARD_IDE_DEVICES+5)<<1) ; XT-CFv3 using DMA
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| 163 | ; Memory Mapped I/O
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| 164 | DEVICE_8BIT_JRIDE_ISA EQU ((COUNT_OF_STANDARD_IDE_DEVICES+6)<<1) ; JR-IDE/ISA (Memory Mapped I/O)
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| 165 | DEVICE_8BIT_ADP50L EQU ((COUNT_OF_STANDARD_IDE_DEVICES+7)<<1) ; SVC ADP50L (Memory Mapped I/O)
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| 166 | ; Virtual devices
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| 167 | DEVICE_SERIAL_PORT EQU (COUNT_OF_ALL_IDE_DEVICES<<1)
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| 168 |
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| 169 |
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| 170 |
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| 171 | ; Master/Slave drive specific parameters
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| 172 | struc DRVPARAMS
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| 173 | .wFlags resb 2 ; Drive flags
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| 174 | .dwMaximumLBA: ; User specified maximum number of sectors
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| 175 | .wCylinders resb 2 ; User specified cylinders (1...16383)
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| 176 | .wHeadsAndSectors:
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| 177 | .bHeads resb 1 ; User specified Heads (1...16)
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| 178 | .bSect resb 1 ; User specified Sectors per track (1...63)
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| 179 | endstruc
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| 180 |
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| 181 | ; Bit defines for DRVPARAMS.wFlags
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| 182 | MASK_DRVPARAMS_WRITECACHE EQU (3<<0) ; Bits 0...1, Drive internal write cache settings (must start at bit 0)
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| 183 | DEFAULT_WRITE_CACHE EQU 0 ; Must be 0
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| 184 | DISABLE_WRITE_CACHE EQU 1
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| 185 | ENABLE_WRITE_CACHE EQU 2
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| 186 | MASK_DRVPARAMS_TRANSLATEMODE EQU (3<<TRANSLATEMODE_FIELD_POSITION) ; Bits 2...3, Position shared with DPT
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| 187 | TRANSLATEMODE_FIELD_POSITION EQU 2
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| 188 | TRANSLATEMODE_NORMAL EQU 0 ; Must be zero
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| 189 | TRANSLATEMODE_LARGE EQU 1
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| 190 | TRANSLATEMODE_ASSISTED_LBA EQU 2 ; 28-bit or 48-bit LBA
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| 191 | TRANSLATEMODE_AUTO EQU 3 ; Only available in ROMVARS, not in DPTs
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| 192 | FLG_DRVPARAMS_BLOCKMODE EQU (1<<4) ; Enable Block mode transfers
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| 193 | FLG_DRVPARAMS_USERCHS EQU (1<<5) ; User specified P-CHS values
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| 194 | MAX_PCHS_CYLINDERS EQU 16383
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| 195 | MAX_PCHS_HEADS EQU 16
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| 196 | MAX_PCHS_SECTORS_PER_TRACK EQU 63
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| 197 | MAX_PCHS_TOTAL_SECTOR_COUNT EQU (MAX_PCHS_CYLINDERS * MAX_PCHS_HEADS * MAX_PCHS_SECTORS_PER_TRACK) ; 16,514,064
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| 198 | FLG_DRVPARAMS_USERLBA EQU (1<<6) ; User specified LBA value
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| 199 |
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| 200 | %endif ; ROMVARS_INC
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