source: xtideuniversalbios/trunk/XTIDE_Universal_BIOS/Inc/RomVars.inc@ 90

Last change on this file since 90 was 90, checked in by Tomi Tilli, 14 years ago

Changes to XTIDE Universal BIOS:

  • Removed INT 13h format and diagnostics functions.
  • Removed INT 18h callback handler.
  • Removed configuration for early/late initialization. Now XT builds always use late and AT build early initialization.
  • Reduced number of supported IDE controllers from 5 to 4.
  • Removed reserved configuration bytes.
  • Removed simple and system boot loaders.
File size: 2.5 KB
Line 
1; Project name : XTIDE Universal BIOS
2; Description : Defines for ROMVARS struct containing variables stored
3; in BIOS ROM.
4%ifndef ROMVARS_INC
5%define ROMVARS_INC
6
7; ROM Variables. There are written to ROM image before flashing.
8struc ROMVARS
9 .wRomSign resb 2 ; ROM Signature (AA55h)
10 .bRomSize resb 1 ; ROM size in 512 byte blocks
11 .rgbJump resb 3 ; First instruction to ROM init (jmp)
12
13 .rgbSign resb 8 ; Signature for XTIDE Configurator Program
14 .szTitle resb 31 ; BIOS title string
15 .szVersion resb 23 ; BIOS version string
16
17 .wFlags resb 2 ; Word for ROM flags
18 .bIdeCnt resb 1 ; Number of available IDE controllers
19 .bBootDrv resb 1 ; Boot Menu default drive
20 .bBootDelay resb 1 ; Boot Menu selection delay in seconds
21 .bMinFddCnt resb 1 ; Minimum number of Floppy Drives
22 .bStealSize resb 1 ; Number of 1kB blocks stolen from 640kB base RAM
23
24 .ideVars0 resb IDEVARS_size
25 .ideVars1 resb IDEVARS_size
26 .ideVars2 resb IDEVARS_size
27 .ideVars3 resb IDEVARS_size
28endstruc
29
30; Bit defines for ROMVARS.wFlags
31FLG_ROMVARS_FULLMODE EQU (1<<0) ; Full operating mode (steals base RAM, supports EBIOS etc.)
32FLG_ROMVARS_DRVXLAT EQU (1<<2) ; Enable drive number translation
33FLG_ROMVARS_ROMBOOT EQU (1<<3) ; Include ROMBOOT to boot menu
34FLG_ROMVARS_MAXSIZE EQU (1<<5) ; Maximize size by sacrificing compatibility with some old BIOSes
35
36
37; Controller specific variables
38struc IDEVARS
39 .wPort resb 2 ; IDE Base Port for Command Block (usual) Registers
40 .wPortCtrl resb 2 ; IDE Base Port for Control Block Registers
41 .bBusType resb 1 ; Bus type
42 .bIRQ resb 1 ; Interrupt Request Number
43 .drvParamsMaster resb DRVPARAMS_size
44 .drvParamsSlave resb DRVPARAMS_size
45endstruc
46
47; Bus types for IDEVARS.bBusType
48BUS_TYPE_8_DUAL EQU (0<<1) ; XTIDE transfers with two 8-bit data ports
49BUS_TYPE_16 EQU (1<<1) ; Normal 16-bit AT-IDE transfers
50BUS_TYPE_32 EQU (2<<1) ; 32-bit VLB and PCI transfers
51BUS_TYPE_8_SINGLE EQU (3<<1) ; 8-bit transfers with single 8-bit data port
52
53
54; Master/Slave drive specific parameters
55struc DRVPARAMS
56 .wFlags resb 2 ; Drive flags
57 .wCylinders resb 2 ; User specified cylinders (1...16383)
58 .wSectAndHeads:
59 .bSect resb 1 ; User specified Sectors per track (1...63)
60 .bHeads resb 1 ; User specified Heads (1...16)
61endstruc
62
63; Bit defines for DRVPARAMS.wFlags
64FLG_DRVPARAMS_USERCHS EQU (1<<0) ; User specified P-CHS values
65FLG_DRVPARAMS_BLOCKMODE EQU (1<<1) ; Enable Block mode transfers
66
67
68%endif ; ROMVARS_INC
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