| [3] | 1 | ; File name : IdeRegisters.inc
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| 2 | ; Project name : IDE BIOS
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| 3 | ; Created date : 23.3.2010
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| 4 | ; Last update : 23.3.2010
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| 5 | ; Author : Tomi Tilli
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| 6 | ; Description : Equates for IDE registers, flags and commands.
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| 7 | %ifndef IDEREGISTERS_INC
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| 8 | %define IDEREGISTERS_INC
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| 9 |
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| 10 | ; IDE Register offsets from Command Block base port
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| 11 | REG_IDE_DATA EQU 0 ; Data Register
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| 12 | REGR_IDE_ERROR EQU 1 ; Error Register
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| 13 | REGW_IDE_FEAT EQU 1 ; Features Register (ATA1+)
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| 14 | ;REGW_IDE_WRPC EQU 1 ; Write Precompensation Register (obsolete on ATA1+)
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| 15 | REG_IDE_CNT EQU 2 ; Sector Count Register
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| 16 | REG_IDE_SECT EQU 3 ; Sector Number Register (LBA 7...0)
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| 17 | REG_IDE_LBA_LOW EQU 3 ; LBA Low Register
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| 18 | REG_IDE_LOCYL EQU 4 ; Low Cylinder Register (LBA 15...8)
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| 19 | REG_IDE_LBA_MID EQU 4 ; LBA Mid Register
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| 20 | REG_IDE_HICYL EQU 5 ; High Cylinder Register (LBA 23...16)
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| 21 | REG_IDE_LBA_HIGH EQU 5 ; LBA High Register
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| 22 | REG_IDE_DRVHD EQU 6 ; Drive and Head Register (LBA 27...24)
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| 23 | REGR_IDE_ST EQU 7 ; Status Register
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| 24 | REGW_IDE_CMD EQU 7 ; Command Register
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| 25 | REG_IDE_HIDATA EQU 8 ; XTIDE Data High Register (actually first Control Block reg)
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| 26 |
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| 27 | ; IDE Register offsets from Control Block base port
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| 28 | ; (usually Command Block base port + 200h)
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| 29 | REGR_IDEC_AST EQU 6 ; Alternate Status Register
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| 30 | REGW_IDEC_CTRL EQU 6 ; Device Control Register
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| 31 | ;REGR_IDEC_ADDR EQU 7 ; Drive Address Register (obsolete on ATA2+)
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| 32 |
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| 33 |
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| 34 | ; Bit definitions for IDE Error Register
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| 35 | FLG_IDE_ERR_BBK EQU (1<<7) ; Bad Block Detected (reserved on ATA2+, command dependent on ATA4+)
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| 36 | FLG_IDE_ERR_UNC EQU (1<<6) ; Uncorrectable Data Error (command dependent on ATA4+)
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| 37 | FLG_IDE_ERR_MC EQU (1<<5) ; Media Changed (command dependent on ATA4+)
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| 38 | FLG_IDE_ERR_IDNF EQU (1<<4) ; ID Not Found (command dependent on ATA4+)
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| 39 | FLG_IDE_ERR_MCR EQU (1<<3) ; Media Change Request (command dependent on ATA4+)
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| 40 | FLG_IDE_ERR_ABRT EQU (1<<2) ; Command Aborted
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| 41 | FLG_IDE_ERR_TK0NF EQU (1<<1) ; Track 0 Not Found (command dependent on ATA4+)
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| 42 | FLG_IDE_ERR_AMNF EQU (1<<0) ; Address Mark Not Found (command dependent on ATA4+)
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| 43 |
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| 44 | ; Bit definitions for IDE Drive and Head Select Register
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| 45 | FLG_IDE_DRVHD_LBA EQU (1<<6) ; LBA Addressing enabled (instead of CHS)
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| 46 | FLG_IDE_DRVHD_DRV EQU (1<<4) ; Drive Select (0=Master, 1=Slave)
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| 47 | MASK_IDE_DRVHD_HEAD EQU 0Fh ; Head select bits (bits 0...3)
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| 48 | MASK_IDE_DRVHD_SET EQU 0A0h ; Bits that must be set to 1 on ATA1 (reserved on ATA2+)
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| 49 |
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| 50 | ; Bit definitions for IDE Status Register
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| 51 | FLG_IDE_ST_BSY EQU (1<<7) ; Busy (other flags undefined when set)
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| 52 | FLG_IDE_ST_DRDY EQU (1<<6) ; Device Ready
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| 53 | FLG_IDE_ST_DF EQU (1<<5) ; Device Fault (command dependent on ATA4+)
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| 54 | FLG_IDE_ST_DSC EQU (1<<4) ; Device Seek Complete (command dependent on ATA4+)
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| 55 | FLG_IDE_ST_DRQ EQU (1<<3) ; Data Request
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| 56 | FLG_IDE_ST_CORR EQU (1<<2) ; Corrected Data (obsolete on ATA4+)
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| 57 | FLG_IDE_ST_IDX EQU (1<<1) ; Index (vendor specific on ATA2+, obsolete on ATA4+)
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| 58 | FLG_IDE_ST_ERR EQU (1<<0) ; Error
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| 59 |
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| 60 | ; Bit definitions for IDE Device Control Register
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| 61 | ; Bit 0 must be zero, unlisted bits are reserved.
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| 62 | FLG_IDE_CTRL_O8H EQU (1<<3) ; Drive has more than 8 heads (pre-ATA only, 1 on ATA1, reserved on ATA2+)
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| 63 | FLG_IDE_CTRL_SRST EQU (1<<2) ; Software Reset
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| 64 | FLG_IDE_CTRL_nIEN EQU (1<<1) ; Negated Interrupt Enable (IRQ disabled when set)
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| 65 |
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| 66 |
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| 67 | ; Commands for IDE Controller
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| 68 | ;HCMD_RECALIBRATE EQU 10h ; Recalibrate
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| 69 | HCMD_READ_SECT EQU 20h ; Read Sectors (with retries)
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| 70 | HCMD_WRITE_SECT EQU 30h ; Write Sectors (with retries)
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| 71 | HCMD_VERIFY_SECT EQU 40h ; Read Verify Sectors (with retries)
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| 72 | ;HCMD_FORMAT EQU 50h ; Format track
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| 73 | HCMD_SEEK EQU 70h ; Seek
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| 74 | ;HCMD_DIAGNOSTIC EQU 90h ; Execute Device Diagnostic
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| 75 | HCMD_INIT_DEV EQU 91h ; Initialize Device Parameters
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| 76 | HCMD_READ_MUL EQU 0C4h ; Read Multiple (=block)
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| 77 | HCMD_WRITE_MUL EQU 0C5h ; Write Multiple (=block)
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| 78 | HCMD_SET_MUL EQU 0C6h ; Set Multiple Mode (=block size)
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| 79 | HCMD_ID_DEV EQU 0ECh ; Identify Device
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| 80 | HCMD_SET_FEAT EQU 0EFh ; Set Features
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| 81 |
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| 82 | ; Set Features subcommands
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| 83 | HFEAT_SET_XFER_MODE EQU 03h ; Set transfer mode based on value in Sector Count register
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| 84 |
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| 85 |
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| 86 | %endif ; IDEREGISTERS_INC
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