| [150] | 1 | ; Project name : XTIDE Universal BIOS
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| [3] | 2 | ; Description : Equates for IDE registers, flags and commands.
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| [376] | 3 |
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| 4 | ;
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| [380] | 5 | ; XTIDE Universal BIOS and Associated Tools
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| [526] | 6 | ; Copyright (C) 2009-2010 by Tomi Tilli, 2011-2013 by XTIDE Universal BIOS Team.
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| [376] | 7 | ;
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| 8 | ; This program is free software; you can redistribute it and/or modify
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| 9 | ; it under the terms of the GNU General Public License as published by
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| 10 | ; the Free Software Foundation; either version 2 of the License, or
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| 11 | ; (at your option) any later version.
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| [380] | 12 | ;
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| [376] | 13 | ; This program is distributed in the hope that it will be useful,
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| 14 | ; but WITHOUT ANY WARRANTY; without even the implied warranty of
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| 15 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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| [380] | 16 | ; GNU General Public License for more details.
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| [376] | 17 | ; Visit http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
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| 18 | ;
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| 19 |
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| [3] | 20 | %ifndef IDEREGISTERS_INC
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| 21 | %define IDEREGISTERS_INC
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| 22 |
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| 23 | ; IDE Register offsets from Command Block base port
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| [150] | 24 | DATA_REGISTER EQU 0
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| 25 | ERROR_REGISTER_in EQU 1 ; Read only
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| 26 | FEATURES_REGISTER_out EQU 1 ; Write only, ATA1+
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| 27 | ;WRITE_PRECOMPENSATION_out EQU 1 ; Write only, Obsolete on ATA1+
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| 28 | SECTOR_COUNT_REGISTER EQU 2
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| 29 | SECTOR_NUMBER_REGISTER EQU 3 ; LBA Low Register
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| 30 | LOW_CYLINDER_REGISTER EQU 4 ; LBA Middle Register
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| 31 | HIGH_CYLINDER_REGISTER EQU 5 ; LBA High Register
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| 32 | LBA_LOW_REGISTER EQU 3 ; LBA 7...0, LBA48 31...24
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| 33 | LBA_MIDDLE_REGISTER EQU 4 ; LBA 15...8, LBA48 39...32
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| 34 | LBA_HIGH_REGISTER EQU 5 ; LBA 23...16, LBA48 47...40
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| 35 | DRIVE_AND_HEAD_SELECT_REGISTER EQU 6 ; LBA28 27...24
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| 36 | STATUS_REGISTER_in EQU 7 ; Read only
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| 37 | COMMAND_REGISTER_out EQU 7 ; Write only
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| [158] | 38 | ;XTIDE_DATA_HIGH_REGISTER EQU 8 ; Non-standard (actually first Control Block reg)
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| [3] | 39 |
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| 40 | ; IDE Register offsets from Control Block base port
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| 41 | ; (usually Command Block base port + 200h)
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| [150] | 42 | ALTERNATE_STATUS_REGISTER_in EQU 6 ; Read only
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| 43 | DEVICE_CONTROL_REGISTER_out EQU 6 ; Write only
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| 44 | ;DRIVE_ADDRESS_REGISTER EQU 7 ; Obsolete on ATA2+
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| [3] | 45 |
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| [150] | 46 | ; Bit mask for XTIDE mod with reversed A0 and A3 address lines
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| 47 | MASK_A3_AND_A0_ADDRESS_LINES EQU ((1<<3) | (1<<0))
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| [3] | 48 |
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| 49 | ; Bit definitions for IDE Error Register
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| [150] | 50 | FLG_ERROR_BBK EQU (1<<7) ; Bad Block Detected (reserved on ATA2+, command dependent on ATA4+)
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| 51 | FLG_ERROR_UNC EQU (1<<6) ; Uncorrectable Data Error (command dependent on ATA4+)
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| 52 | FLG_ERROR_MC EQU (1<<5) ; Media Changed (command dependent on ATA4+)
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| 53 | FLG_ERROR_IDNF EQU (1<<4) ; ID Not Found (command dependent on ATA4+)
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| 54 | FLG_ERROR_MCR EQU (1<<3) ; Media Change Request (command dependent on ATA4+)
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| 55 | FLG_ERROR_ABRT EQU (1<<2) ; Command Aborted
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| 56 | FLG_ERROR_TK0NF EQU (1<<1) ; Track 0 Not Found (command dependent on ATA4+)
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| 57 | FLG_ERROR_AMNF EQU (1<<0) ; Address Mark Not Found (command dependent on ATA4+)
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| [3] | 58 |
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| 59 | ; Bit definitions for IDE Drive and Head Select Register
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| [150] | 60 | FLG_DRVNHEAD_LBA EQU (1<<6) ; LBA Addressing enabled (instead of CHS)
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| 61 | FLG_DRVNHEAD_DRV EQU (1<<4) ; Drive Select (0=Master, 1=Slave)
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| 62 | MASK_DRVNHEAD_HEAD EQU 0Fh ; Head select bits (bits 0...3)
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| 63 | MASK_DRVNHEAD_SET EQU 0A0h ; Bits that must be set to 1 on ATA1 (reserved on ATA2+)
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| [3] | 64 |
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| 65 | ; Bit definitions for IDE Status Register
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| [150] | 66 | FLG_STATUS_BSY EQU (1<<7) ; Busy (other flags undefined when set)
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| 67 | FLG_STATUS_DRDY EQU (1<<6) ; Device Ready
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| 68 | FLG_STATUS_DF EQU (1<<5) ; Device Fault (command dependent on ATA4+)
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| 69 | FLG_STATUS_DSC EQU (1<<4) ; Device Seek Complete (command dependent on ATA4+)
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| 70 | FLG_STATUS_DRQ EQU (1<<3) ; Data Request
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| 71 | FLG_STATUS_CORR EQU (1<<2) ; Corrected Data (obsolete on ATA4+)
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| 72 | FLG_STATUS_IDX EQU (1<<1) ; Index (vendor specific on ATA2+, obsolete on ATA4+)
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| 73 | FLG_STATUS_ERR EQU (1<<0) ; Error
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| [3] | 74 |
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| 75 | ; Bit definitions for IDE Device Control Register
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| 76 | ; Bit 0 must be zero, unlisted bits are reserved.
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| [158] | 77 | ;FLG_DEVCONTROL_HOB EQU (1<<7) ; High Order Byte (ATA6+)
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| [541] | 78 | FLG_DEVCONTROL_O8H EQU (1<<3) ; Drive has more than 8 heads (pre-ATA only, 1 on ATA1, reserved on ATA2+)
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| [150] | 79 | FLG_DEVCONTROL_SRST EQU (1<<2) ; Software Reset
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| 80 | FLG_DEVCONTROL_nIEN EQU (1<<1) ; Negated Interrupt Enable (IRQ disabled when set)
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| [3] | 81 |
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| 82 | ; Commands for IDE Controller
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| [365] | 83 | COMMAND_RECALIBRATE EQU 10h
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| [150] | 84 | COMMAND_READ_SECTORS EQU 20h
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| 85 | COMMAND_READ_SECTORS_EXT EQU 24h ; LBA48
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| 86 | COMMAND_WRITE_SECTORS EQU 30h
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| 87 | COMMAND_WRITE_SECTORS_EXT EQU 34h ; LBA48
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| 88 | COMMAND_VERIFY_SECTORS EQU 40h
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| 89 | COMMAND_VERIFY_SECTORS_EXT EQU 42h ; LBA48
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| 90 | COMMAND_SEEK EQU 70h
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| 91 | COMMAND_INITIALIZE_DEVICE_PARAMETERS EQU 91h
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| 92 | COMMAND_SET_MULTIPLE_MODE EQU 0C6h ; Block mode
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| 93 | COMMAND_READ_MULTIPLE EQU 0C4h ; Block mode
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| 94 | COMMAND_READ_MULTIPLE_EXT EQU 29h ; LBA48, Block mode
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| 95 | COMMAND_WRITE_MULTIPLE EQU 0C5h ; Block mode
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| 96 | COMMAND_WRITE_MULTIPLE_EXT EQU 39h ; LBA48, Block mode
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| 97 | COMMAND_IDENTIFY_DEVICE EQU 0ECh
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| 98 | COMMAND_SET_FEATURES EQU 0EFh
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| [615] | 99 | COMMAND_STAND_BY EQU 0E2h
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| [380] | 100 | COMMAND_IDLE EQU 0E3h
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| [3] | 101 |
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| 102 |
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| [276] | 103 | ; Subcommands for COMMAND_SET_FEATURES
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| [618] | 104 | FEATURE_ENABLE_8BIT_PIO_TRANSFER_MODE EQU 01h ; CFA feature set only
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| 105 | FEATURE_ENABLE_WRITE_CACHE EQU 02h
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| 106 | FEATURE_ENABLE_ADVANCED_POWER_MANAGEMENT EQU 05h
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| 107 | FEATURE_DISABLE_8BIT_PIO_TRANSFER_MODE EQU 81h ; CFA feature set only
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| 108 | FEATURE_DISABLE_WRITE_CACHE EQU 82h ; Can also be used to flush cache
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| 109 | FEATURE_DISABLE_ADVANCED_POWER_MANAGEMENT EQU 85h ; Might not be supported even if FEATURE_ENABLE_ADVANCED_POWER_MANAGEMENT is
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| 110 | FEATURE_SET_TRANSFER_MODE EQU 03h ; Transfer mode goes to the Sector Count Register
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| 111 | PIO_DEFAULT_MODE EQU 0h
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| 112 | PIO_DEFAULT_MODE_DISABLE_IORDY EQU 1h
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| 113 | PIO_FLOW_CONTROL_MODE_xxx EQU (1<<3) ; Bits 2...0 hold the PIO mode
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| [276] | 114 |
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| 115 |
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| [3] | 116 | %endif ; IDEREGISTERS_INC
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