source: xtideuniversalbios/trunk/XTIDE_Universal_BIOS/Inc/IdeRegisters.inc@ 401

Last change on this file since 401 was 380, checked in by krille_n_@…, 13 years ago

Changes:

  • Added code to XTIDECFG for Power Management (standby timer) support in the BIOS.
  • Some minor optimizations.
File size: 5.1 KB
RevLine 
[150]1; Project name : XTIDE Universal BIOS
[3]2; Description : Equates for IDE registers, flags and commands.
[376]3
4;
[380]5; XTIDE Universal BIOS and Associated Tools
[376]6; Copyright (C) 2009-2010 by Tomi Tilli, 2011-2012 by XTIDE Universal BIOS Team.
7;
8; This program is free software; you can redistribute it and/or modify
9; it under the terms of the GNU General Public License as published by
10; the Free Software Foundation; either version 2 of the License, or
11; (at your option) any later version.
[380]12;
[376]13; This program is distributed in the hope that it will be useful,
14; but WITHOUT ANY WARRANTY; without even the implied warranty of
15; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
[380]16; GNU General Public License for more details.
[376]17; Visit http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
18;
19
[3]20%ifndef IDEREGISTERS_INC
21%define IDEREGISTERS_INC
22
23; IDE Register offsets from Command Block base port
[150]24DATA_REGISTER EQU 0
25ERROR_REGISTER_in EQU 1 ; Read only
26FEATURES_REGISTER_out EQU 1 ; Write only, ATA1+
27;WRITE_PRECOMPENSATION_out EQU 1 ; Write only, Obsolete on ATA1+
28SECTOR_COUNT_REGISTER EQU 2
29SECTOR_NUMBER_REGISTER EQU 3 ; LBA Low Register
30LOW_CYLINDER_REGISTER EQU 4 ; LBA Middle Register
31HIGH_CYLINDER_REGISTER EQU 5 ; LBA High Register
32LBA_LOW_REGISTER EQU 3 ; LBA 7...0, LBA48 31...24
33LBA_MIDDLE_REGISTER EQU 4 ; LBA 15...8, LBA48 39...32
34LBA_HIGH_REGISTER EQU 5 ; LBA 23...16, LBA48 47...40
35DRIVE_AND_HEAD_SELECT_REGISTER EQU 6 ; LBA28 27...24
36STATUS_REGISTER_in EQU 7 ; Read only
37COMMAND_REGISTER_out EQU 7 ; Write only
[158]38;XTIDE_DATA_HIGH_REGISTER EQU 8 ; Non-standard (actually first Control Block reg)
[3]39
40; IDE Register offsets from Control Block base port
41; (usually Command Block base port + 200h)
[150]42ALTERNATE_STATUS_REGISTER_in EQU 6 ; Read only
43DEVICE_CONTROL_REGISTER_out EQU 6 ; Write only
44;DRIVE_ADDRESS_REGISTER EQU 7 ; Obsolete on ATA2+
[3]45
[150]46; Bit mask for XTIDE mod with reversed A0 and A3 address lines
47MASK_A3_AND_A0_ADDRESS_LINES EQU ((1<<3) | (1<<0))
[3]48
49; Bit definitions for IDE Error Register
[150]50FLG_ERROR_BBK EQU (1<<7) ; Bad Block Detected (reserved on ATA2+, command dependent on ATA4+)
51FLG_ERROR_UNC EQU (1<<6) ; Uncorrectable Data Error (command dependent on ATA4+)
52FLG_ERROR_MC EQU (1<<5) ; Media Changed (command dependent on ATA4+)
53FLG_ERROR_IDNF EQU (1<<4) ; ID Not Found (command dependent on ATA4+)
54FLG_ERROR_MCR EQU (1<<3) ; Media Change Request (command dependent on ATA4+)
55FLG_ERROR_ABRT EQU (1<<2) ; Command Aborted
56FLG_ERROR_TK0NF EQU (1<<1) ; Track 0 Not Found (command dependent on ATA4+)
57FLG_ERROR_AMNF EQU (1<<0) ; Address Mark Not Found (command dependent on ATA4+)
[3]58
59; Bit definitions for IDE Drive and Head Select Register
[150]60FLG_DRVNHEAD_LBA EQU (1<<6) ; LBA Addressing enabled (instead of CHS)
61FLG_DRVNHEAD_DRV EQU (1<<4) ; Drive Select (0=Master, 1=Slave)
62MASK_DRVNHEAD_HEAD EQU 0Fh ; Head select bits (bits 0...3)
63MASK_DRVNHEAD_SET EQU 0A0h ; Bits that must be set to 1 on ATA1 (reserved on ATA2+)
[3]64
65; Bit definitions for IDE Status Register
[150]66FLG_STATUS_BSY EQU (1<<7) ; Busy (other flags undefined when set)
67FLG_STATUS_DRDY EQU (1<<6) ; Device Ready
68FLG_STATUS_DF EQU (1<<5) ; Device Fault (command dependent on ATA4+)
69FLG_STATUS_DSC EQU (1<<4) ; Device Seek Complete (command dependent on ATA4+)
70FLG_STATUS_DRQ EQU (1<<3) ; Data Request
71FLG_STATUS_CORR EQU (1<<2) ; Corrected Data (obsolete on ATA4+)
72FLG_STATUS_IDX EQU (1<<1) ; Index (vendor specific on ATA2+, obsolete on ATA4+)
73FLG_STATUS_ERR EQU (1<<0) ; Error
[3]74
75; Bit definitions for IDE Device Control Register
76; Bit 0 must be zero, unlisted bits are reserved.
[158]77;FLG_DEVCONTROL_HOB EQU (1<<7) ; High Order Byte (ATA6+)
[150]78;FLG_DEVCONTROL_O8H EQU (1<<3) ; Drive has more than 8 heads (pre-ATA only, 1 on ATA1, reserved on ATA2+)
79FLG_DEVCONTROL_SRST EQU (1<<2) ; Software Reset
80FLG_DEVCONTROL_nIEN EQU (1<<1) ; Negated Interrupt Enable (IRQ disabled when set)
[3]81
82; Commands for IDE Controller
[365]83COMMAND_RECALIBRATE EQU 10h
[150]84COMMAND_READ_SECTORS EQU 20h
85COMMAND_READ_SECTORS_EXT EQU 24h ; LBA48
86COMMAND_WRITE_SECTORS EQU 30h
87COMMAND_WRITE_SECTORS_EXT EQU 34h ; LBA48
88COMMAND_VERIFY_SECTORS EQU 40h
89COMMAND_VERIFY_SECTORS_EXT EQU 42h ; LBA48
90COMMAND_SEEK EQU 70h
91COMMAND_INITIALIZE_DEVICE_PARAMETERS EQU 91h
92COMMAND_SET_MULTIPLE_MODE EQU 0C6h ; Block mode
93COMMAND_READ_MULTIPLE EQU 0C4h ; Block mode
94COMMAND_READ_MULTIPLE_EXT EQU 29h ; LBA48, Block mode
95COMMAND_WRITE_MULTIPLE EQU 0C5h ; Block mode
96COMMAND_WRITE_MULTIPLE_EXT EQU 39h ; LBA48, Block mode
97COMMAND_IDENTIFY_DEVICE EQU 0ECh
98COMMAND_SET_FEATURES EQU 0EFh
[380]99COMMAND_IDLE EQU 0E3h
[3]100
101
[276]102; Subcommands for COMMAND_SET_FEATURES
103FEATURE_ENABLE_WRITE_CACHE EQU 02h
104FEATURE_DISABLE_WRITE_CACHE EQU 82h ; Can also be used to flush cache
[380]105FEATURE_SET_TRANSFER_MODE EQU 03h ; Transfer mode goes to the Sector Count Register
[363]106 PIO_DEFAULT_MODE EQU 0h
107 PIO_DEFAULT_MODE_DISABLE_IORDY EQU 1h
108 PIO_FLOW_CONTROL_MODE_xxx EQU (1<<3) ; Bits 2...0 hold the PIO mode
[276]109
110
[3]111%endif ; IDEREGISTERS_INC
Note: See TracBrowser for help on using the repository browser.