source: xtideuniversalbios/trunk/XTIDE_Universal_BIOS/Inc/DmaController.inc@ 478

Last change on this file since 478 was 477, checked in by aitotat@…, 12 years ago

Changes to XTIDE Universal BIOS:

  • Added non-working DMA transfer code.
File size: 7.3 KB
Line 
1; Project name : XTIDE Universal BIOS
2; Description : Equates for 8237 DMA Controllers.
3
4;
5; XTIDE Universal BIOS and Associated Tools
6; Copyright (C) 2009-2010 by Tomi Tilli, 2011-2012 by XTIDE Universal BIOS Team.
7;
8; This program is free software; you can redistribute it and/or modify
9; it under the terms of the GNU General Public License as published by
10; the Free Software Foundation; either version 2 of the License, or
11; (at your option) any later version.
12;
13; This program is distributed in the hope that it will be useful,
14; but WITHOUT ANY WARRANTY; without even the implied warranty of
15; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16; GNU General Public License for more details.
17; Visit http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
18;
19
20%ifndef DMA_CONTROLLER_INC
21%define DMA_CONTROLLER_INC
22
23; 8237 Master (8-bit) and Slave (16-bit) DMA Controller Ports
24
25; Page Registers
26PAGE_DMA8_CH_1 EQU 83h
27PAGE_DMA8_CH_2 EQU 81h
28PAGE_DMA8_CH_3 EQU 82h
29PAGE_DMA16_CH_5 EQU 8Bh ; AT+
30PAGE_DMA16_CH_6 EQU 89h ; AT+
31PAGE_DMA16_CH_7 EQU 8Ah ; AT+
32
33; Base and Current Address Registers
34BASE_AND_CURRENT_ADDRESS_REGISTER_DMA8_CH1_out EQU 02h
35BASE_AND_CURRENT_ADDRESS_REGISTER_DMA8_CH2_out EQU 04h
36BASE_AND_CURRENT_ADDRESS_REGISTER_DMA8_CH3_out EQU 06h
37BASE_AND_CURRENT_ADDRESS_REGISTER_DMA16_CH5_out EQU 0C4h ; AT+
38BASE_AND_CURRENT_ADDRESS_REGISTER_DMA16_CH6_out EQU 0C8h ; AT+
39BASE_AND_CURRENT_ADDRESS_REGISTER_DMA16_CH7_out EQU 0CCh ; AT+
40CURRENT_ADDRESS_REGISTER_DMA8_CH1_in EQU 02h
41CURRENT_ADDRESS_REGISTER_DMA8_CH2_in EQU 04h
42CURRENT_ADDRESS_REGISTER_DMA8_CH3_in EQU 06h
43CURRENT_ADDRESS_REGISTER_DMA16_CH5_in EQU 0C4h ; AT+
44CURRENT_ADDRESS_REGISTER_DMA16_CH6_in EQU 0C8h ; AT+
45CURRENT_ADDRESS_REGISTER_DMA16_CH7_in EQU 0CCh ; AT+
46
47; Base and Current Count Registers
48BASE_AND_CURRENT_COUNT_REGISTER_DMA8_CH1_out EQU 03h
49BASE_AND_CURRENT_COUNT_REGISTER_DMA8_CH2_out EQU 05h
50BASE_AND_CURRENT_COUNT_REGISTER_DMA8_CH3_out EQU 07h
51BASE_AND_CURRENT_COUNT_REGISTER_DMA16_CH5_out EQU 0C6h ; AT+
52BASE_AND_CURRENT_COUNT_REGISTER_DMA16_CH6_out EQU 0CAh ; AT+
53BASE_AND_CURRENT_COUNT_REGISTER_DMA16_CH7_out EQU 0CEh ; AT+
54CURRENT_COUNT_REGISTER_DMA8_CH1_in EQU 03h
55CURRENT_COUNT_REGISTER_DMA8_CH2_in EQU 05h
56CURRENT_COUNT_REGISTER_DMA8_CH3_in EQU 07h
57CURRENT_COUNT_REGISTER_DMA16_CH5_in EQU 0C6h ; AT+
58CURRENT_COUNT_REGISTER_DMA16_CH6_in EQU 0CAh ; AT+
59CURRENT_COUNT_REGISTER_DMA16_CH7_in EQU 0CEh ; AT+
60
61; Command Registers (Command Value used by PCs is 0)
62COMMAND_REGISTER_DMA8_out EQU 08h
63COMMAND_REGISTER_DMA16_out EQU 0D0h ; AT+
64 MEM_TO_MEM_XFERS_DISABLE EQU 0
65 MEM_TO_MEM_XFERS_ENABLE EQU (1<<0)
66
67 CH0_ADDRESS_HOLD_DISABLE EQU 0
68 CH0_ADDRESS_HOLD_ENABLE EQU (1<<1) ; When MEM_TO_MEM_XFERS_ENABLE
69
70 CONTROLLER_ENABLE EQU 0
71 CONTROLLER_DISABLE EQU (1<<2) ; Instead of Controller Enable
72
73 NORMAL_TIMING EQU 0
74 COMPRESSED_TIMING EQU (1<<3) ; Instead of Normal Timing when MEM_TO_MEM_XFERS_DISABLE
75
76 FIXED_PRIORITY EQU 0
77 ROTATING_PRIORITY EQU (1<<4) ; Instead of Fixed Priority
78
79 LATE_WRITE_SELECTION EQU 0
80 EXTENDED_WRITE_SELECTION EQU (1<<5) ; Instead of Late Write Selection
81
82 DREQ_SENSE_ACTIVE_HIGH EQU 0
83 DREQ_SENSE_ACTIVE_LOW EQU (1<<6) ; Instead of DREQ Sense Active High
84
85 DACK_SENSE_ACTIVE_LOW EQU 0
86 DACK_SENSE_ACTIVE_HIGH EQU (1<<7) ; Instead of DACK Sense Active Low
87
88
89; Status Registers
90STATUS_REGISTER_DMA8_in EQU COMMAND_REGISTER_DMA8_out
91 FLG_CH1_HAS_REACHED_TERMINAL_COUNT EQU (1<<1)
92 FLG_CH2_HAS_REACHED_TERMINAL_COUNT EQU (1<<2)
93 FLG_CH3_HAS_REACHED_TERMINAL_COUNT EQU (1<<3)
94 FLG_CH1_REQUEST EQU (1<<5)
95 FLG_CH2_REQUEST EQU (1<<6)
96 FLG_CH3_REQUEST EQU (1<<7)
97STATUS_REGISTER_DMA16_in EQU COMMAND_REGISTER_DMA16_out ; AT+
98 FLG_CH5_HAS_REACHED_TERMINAL_COUNT EQU (1<<1)
99 FLG_CH6_HAS_REACHED_TERMINAL_COUNT EQU (1<<2)
100 FLG_CH7_HAS_REACHED_TERMINAL_COUNT EQU (1<<3)
101 FLG_CH5_REQUEST EQU (1<<5)
102 FLG_CH6_REQUEST EQU (1<<6)
103 FLG_CH7_REQUEST EQU (1<<7)
104
105
106; Request Registers (Software DMA Request)
107REQUEST_REGISTER_DMA8_out EQU 09h
108 FLG_SET_REQUEST EQU (1<<2)
109 CLEAR_CH1_REQUEST EQU CHANNEL_1
110 CLEAR_CH2_REQUEST EQU CHANNEL_2
111 CLEAR_CH3_REQUEST EQU CHANNEL_3
112 SET_CH1_REQUEST EQU (CHANNEL_1 | FLG_SET_REQUEST)
113 SET_CH2_REQUEST EQU (CHANNEL_2 | FLG_SET_REQUEST)
114 SET_CH3_REQUEST EQU (CHANNEL_3 | FLG_SET_REQUEST)
115REQUEST_REGISTER_DMA16_out EQU 0D2h ; AT+
116 CLEAR_CH5_REQUEST EQU CLEAR_CH1_REQUEST
117 CLEAR_CH6_REQUEST EQU CLEAR_CH2_REQUEST
118 CLEAR_CH7_REQUEST EQU CLEAR_CH3_REQUEST
119 SET_CH5_REQUEST EQU SET_CH1_REQUEST
120 SET_CH6_REQUEST EQU SET_CH2_REQUEST
121 SET_CH7_REQUEST EQU SET_CH3_REQUEST
122
123
124; Mask Registers (setting a mask bit disables DMA channel)
125MASK_REGISTER_DMA8_out EQU 0Ah
126 FLG_SET_MASK EQU FLG_SET_REQUEST
127 CLEAR_CH1_MASK_BIT EQU CLEAR_CH1_REQUEST
128 CLEAR_CH2_MASK_BIT EQU CLEAR_CH2_REQUEST
129 CLEAR_CH3_MASK_BIT EQU CLEAR_CH3_REQUEST
130 SET_CH1_MASK_BIT EQU SET_CH1_REQUEST
131 SET_CH2_MASK_BIT EQU SET_CH2_REQUEST
132 SET_CH3_MASK_BIT EQU SET_CH3_REQUEST
133MASK_REGISTER_DMA16_out EQU 0D4h ; AT+
134 CLEAR_CH5_MASK_BIT EQU CLEAR_CH5_REQUEST
135 CLEAR_CH6_MASK_BIT EQU CLEAR_CH6_REQUEST
136 CLEAR_CH7_MASK_BIT EQU CLEAR_CH7_REQUEST
137 SET_CH5_MASK_BIT EQU SET_CH5_REQUEST
138 SET_CH6_MASK_BIT EQU SET_CH6_REQUEST
139 SET_CH7_MASK_BIT EQU SET_CH7_REQUEST
140
141
142; Mode Registers
143MODE_REGISTER_DMA8_out EQU 0Bh
144 ; Select channel number (bits 0...1)
145 CHANNEL_1 EQU 1
146 CHANNEL_2 EQU 2
147 CHANNEL_3 EQU 3
148MODE_REGISTER_DMA16_out EQU 0D6h ; AT+
149 CHANNEL_5 EQU CHANNEL_1
150 CHANNEL_6 EQU CHANNEL_2
151 CHANNEL_7 EQU CHANNEL_3
152 ; Transfer type (bits 2...3)
153 VERIFY EQU (0<<2)
154 WRITE EQU (1<<2) ; To memory
155 READ EQU (2<<2) ; From memory
156 ; Autoinitialization enable/disable (bit 4)
157 AUTOINIT_DISABLE EQU 0
158 AUTOINIT_ENABLE EQU (1<<4) ; Instead of autoinitialization disable
159 ; Address increment/decrement select (bit 5)
160 ADDRESS_INCREMENT EQU 0
161 ADDRESS_DECREMENT EQU (1<<5) ; Instead of address increment
162 ; Mode type selection (bits 6...7)
163 DEMAND_MODE EQU (0<<6)
164 SINGLE_MODE EQU (1<<6)
165 BLOCK_MODE EQU (2<<6)
166 CASCADE_MODE EQU (3<<6)
167
168
169; Clear Byte Flip-Flops (any byte resets low/high byte flip-flop to low)
170CLEAR_FLIPFLOP_DMA8_out EQU 0Ch
171CLEAR_FLIPFLOP_DMA16_out EQU 0D8h ; AT+
172
173
174; Temporary Registers
175TEMP_REGISTER_DMA8_in EQU 0Dh
176TEMP_REGISTER_DMA16_in EQU 0DAh ; AT+
177
178
179; Master Clear (any byte does the same as hardware reset)
180MASTER_CLEAR_DMA8_out EQU TEMP_REGISTER_DMA8_in
181MASTER_CLEAR_DMA16_out EQU TEMP_REGISTER_DMA16_in ; AT+
182
183
184; Clear all mask bits (any byte enables all DMA channels)
185CLEAR_ALL_MASK_BITS_DMA8_out EQU 0Eh
186CLEAR_ALL_MASK_BITS_DMA16_out EQU 0DCh ; AT+
187
188
189; Write All Mask Bits
190WRITE_ALL_MASK_BITS_DMA8_out EQU 0Fh
191 ALL_MASK_BITS_SET_CH0 EQU (1<<0)
192 ALL_MASK_BITS_SET_CH1 EQU (1<<CHANNEL_1)
193 ALL_MASK_BITS_SET_CH2 EQU (1<<CHANNEL_2)
194 ALL_MASK_BITS_SET_CH3 EQU (1<<CHANNEL_3)
195WRITE_ALL_MASK_BITS_DMA16_out EQU 0DEh ; AT+
196 ALL_MASK_BITS_SET_CH4 EQU ALL_MASK_BITS_SET_CH0
197 ALL_MASK_BITS_SET_CH5 EQU (1<<CHANNEL_5)
198 ALL_MASK_BITS_SET_CH6 EQU (1<<CHANNEL_6)
199 ALL_MASK_BITS_SET_CH7 EQU (1<<CHANNEL_7)
200
201
202%endif ; DMA_CONTROLLER_INC
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