source: xtideuniversalbios/trunk/XTIDE_Universal_BIOS/Inc/CustomDPT.inc @ 364

Last change on this file since 364 was 364, checked in by aitotat@…, 12 years ago

Changes to XTIDE Universal BIOS:

  • Advanced ATA Module variables are now kept in DPTs.
  • Forced full mode when using Advanced ATA Module.
File size: 4.5 KB
Line 
1; Project name  :   XTIDE Universal BIOS
2; Description   :   Defines for DPT structs containing custom
3;                   Disk Parameter Table used by this BIOS.
4%ifndef CUSTOMDPT_INC
5%define CUSTOMDPT_INC
6
7; Base DPT for all device types
8struc DPT   ; 10 bytes
9    ; General Disk Parameter Table related
10    .wFlags:
11    .bFlagsLow                  resb    1
12    .bFlagsHigh                 resb    1
13    .bIdevarsOffset             resb    1   ; Offset to IDEVARS for this drive
14
15    ; IDE Drive related
16    ; .bLbaHeads and .twLbaSectors are used for LBA addressing only.
17    .bLbaHeads:                 resb    1   ; Number of LBA assisted heads (1...255)
18    .twLbaSectors               resb    2   ; 48-bit sector count for LBA addressing
19
20    ; .wPchsCylinders and .bPchsSectors are used for CHS addressing only.
21    .wPchsCylinders             resb    2   ; Number of P-CHS Cylinders (1...16383)
22    .wPchsHeadsAndSectors:
23    .bPchsHeads                 resb    1   ; Number of P-CHS heads (1...16)
24    .bPchsSectors               resb    1   ; Number of P-CHS Sectors per Track (1...63)
25endstruc
26
27; Bit definitions for DPT.bFlagsLow
28MASKL_DPT_CHS_SHIFT_COUNT       EQU (7<<0)  ; Bits 0...3, P-CHS to L-CHS bit shift count (0...4)
29FLGL_DPT_SLAVE                  EQU FLG_DRVNHEAD_DRV    ; (1<<4), Drive is slave drive
30MASKL_DPT_ADDRESSING_MODE       EQU (3<<5)  ; Bits 5..6, Addressing Mode (bit 6 == FLG_DRVNHEAD_LBA)
31FLGL_DPT_ENABLE_IRQ             EQU (1<<7)
32
33; Bit definitions for DPT.bFlagsHigh
34FLGH_DPT_REVERSED_A0_AND_A3     EQU (1<<0)  ; XTIDE mod, Address lines 0 and 3 reversed
35FLGH_DPT_BLOCK_MODE_SUPPORTED   EQU (1<<1)  ; Use block transfer commands (must be bit 1!)
36%ifdef MODULE_SERIAL
37FLGH_DPT_SERIAL_DEVICE          EQU (1<<2)  ; Serial Port Device
38%endif
39FLGH_DPT_INTERRUPT_IN_SERVICE   EQU (1<<3)  ; Set when waiting for IRQ
40
41; IDE device only
42FLGH_DPT_INITERROR              EQU (1<<7)
43%ifdef MODULE_ADVANCED_ATA
44FLGH_DPT_IORDY                  EQU (1<<6)  ; Controller and Drive supports IORDY
45%endif
46
47; Serial device only
48FLGH_DPT_SERIAL_FLOPPY                      EQU (1<<4)
49FLGH_DPT_SERIAL_FLOPPY_TYPE_MASK            EQU 0e0h
50FLGH_DPT_SERIAL_FLOPPY_TYPE_FIELD_POSITION  EQU 5
51
52; Addressing modes for DPT.wFlags
53ADDRESSING_MODE_FIELD_POSITION  EQU     5
54ADDRESSING_MODE_LCHS            EQU     0   ; L-CHS Addressing Mode (NORMAL in many other BIOSes)
55ADDRESSING_MODE_PCHS            EQU     1   ; P-CHS Addressing Mode (LARGE in many other BIOSes)
56ADDRESSING_MODE_LBA28           EQU     2   ; 28-bit LBA Addressing Mode
57ADDRESSING_MODE_LBA48           EQU     3   ; 48-bit LBA Addressing Mode
58
59
60; DPT for ATA devices
61struc DPT_ATA   ; 10 + 2 bytes = 12 bytes
62    .dpt                        resb    DPT_size
63
64    ; Block size is specified in sectors (1, 2, 4, 8, 16, 32, 64 or 128)
65    .wSetAndMaxBlock:
66    .bSetBlock                  resb    1   ; Current block size (do not set to zero!)
67    .bMaxBlock                  resb    1   ; Maximum block size, 0 = block mode not supported
68endstruc
69
70
71; Additional variables needed to initialize and reset Advanced IDE Controllers.
72; EBDA must be reserved for DPTs when using these!
73%ifdef MODULE_ADVANCED_ATA
74struc DPT_ADVANCED_ATA
75    .dpt_ata                resb    DPT_ATA_size
76    .wControllerID          resb    2   ; Controller specific ID WORD (from Advanced Controller detection)
77    .wControllerBasePort    resb    2   ; Advanced Controller port (not IDE port)
78    .wMinPioCycleTime       resb    2   ; Minimum PIO Cycle Time in ns
79    .bPioMode               resb    1   ; Best supported PIO mode
80    .bDevice                resb    1   ; Device Type from IDEVARS (overrided when 32-bit controller detected)
81endstruc
82%endif
83
84
85; DPT for Serial devices
86%ifdef MODULE_SERIAL
87struc DPT_SERIAL
88    .dpt                        resb    DPT_size
89
90    .wSerialPortAndBaud:
91    .bSerialPort                resb    1   ; Serial connection I/O port address, divided by 4
92    .bSerialBaud                resb    1   ; Serial connection baud rate divisor
93endstruc
94%endif
95
96
97; This is the common size for all DPTs. All DPTs must be equal size.
98%ifdef MODULE_ADVANCED_ATA
99LARGEST_DPT_SIZE                EQU     DPT_ADVANCED_ATA_size
100%else
101LARGEST_DPT_SIZE                EQU     DPT_ATA_size
102%endif
103
104
105; Number of Sectors per Track is fixed to 63 for LBA assist calculation.
106; 1024 cylinders, 256 heads, 63 sectors = 8.4 GB limit (but DOS does not support more than 255 heads)
107MAX_LCHS_CYLINDERS              EQU     1024
108LBA_ASSIST_SPT                  EQU     63
109
110
111;--------------------------------------------------------------------
112; LIMIT_LBA_CYLINDERS_IN_DXAX_TO_LCHS_CYLINDERS
113;   Parameters:
114;       DX:AX:  Number of LBA cylinders
115;   Returns:
116;       AX:     Number of L-CHS cylinders
117;   Corrupts registers:
118;       Nothing
119;--------------------------------------------------------------------
120%macro LIMIT_LBA_CYLINDERS_IN_DXAX_TO_LCHS_CYLINDERS 0
121    test    dx, dx
122    jnz     SHORT %%LoadMaxValueToAX
123    cmp     ax, MAX_LCHS_CYLINDERS
124    jbe     SHORT %%NoNeedToModify
125%%LoadMaxValueToAX:
126    mov     ax, MAX_LCHS_CYLINDERS
127%%NoNeedToModify:
128%endmacro
129
130
131%endif ; CUSTOMDPT_INC
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