source: xtideuniversalbios/trunk/XTIDE_Universal_BIOS/Inc/CustomDPT.inc@ 375

Last change on this file since 375 was 370, checked in by krille_n_@…, 12 years ago

Changes:

  • Added some missing PIO mode timings to ATA_ID.inc (based on info from http://www.singlix.net/specs/cfspc4_0.pdf)
  • Updated Configuration_FullMode.txt but it may need additional changes as the Tandy info doesn't match the wiki.
  • Optimizations.
  • Excluded some unused code from XTIDECFG.
File size: 4.7 KB
Line 
1; Project name : XTIDE Universal BIOS
2; Description : Defines for DPT structs containing custom
3; Disk Parameter Table used by this BIOS.
4%ifndef CUSTOMDPT_INC
5%define CUSTOMDPT_INC
6
7; Base DPT for all device types
8struc DPT ; 10 bytes
9 ; General Disk Parameter Table related
10 .wFlags:
11 .bFlagsLow resb 1
12 .bFlagsHigh resb 1
13 .bIdevarsOffset resb 1 ; Offset to IDEVARS for this drive
14
15 ; IDE Drive related
16 ; .bLbaHeads and .twLbaSectors are used for LBA addressing only.
17 .bLbaHeads: resb 1 ; Number of LBA assisted heads (1...255)
18 .twLbaSectors resb 2 ; 48-bit sector count for LBA addressing
19
20 ; .wPchsCylinders and .bPchsSectors are used for CHS addressing only.
21 .wPchsCylinders resb 2 ; Number of P-CHS Cylinders (1...16383)
22 .wPchsHeadsAndSectors:
23 .bPchsHeads resb 1 ; Number of P-CHS heads (1...16)
24 .bPchsSectors resb 1 ; Number of P-CHS Sectors per Track (1...63)
25endstruc
26
27; Bit definitions for DPT.bFlagsLow
28MASKL_DPT_CHS_SHIFT_COUNT EQU (7<<0) ; Bits 0...3, P-CHS to L-CHS bit shift count (0...4)
29FLGL_DPT_SLAVE EQU FLG_DRVNHEAD_DRV ; (1<<4), Drive is slave drive
30MASKL_DPT_ADDRESSING_MODE EQU (3<<5) ; Bits 5..6, Addressing Mode (bit 6 == FLG_DRVNHEAD_LBA)
31FLGL_DPT_ENABLE_IRQ EQU (1<<7)
32
33; Bit definitions for DPT.bFlagsHigh
34FLGH_DPT_REVERSED_A0_AND_A3 EQU (1<<0) ; XTIDE mod, Address lines 0 and 3 reversed
35FLGH_DPT_BLOCK_MODE_SUPPORTED EQU (1<<1) ; Use block transfer commands (must be bit 1!)
36%ifdef MODULE_SERIAL
37FLGH_DPT_SERIAL_DEVICE EQU (1<<2) ; Serial Port Device
38%endif
39FLGH_DPT_INTERRUPT_IN_SERVICE EQU (1<<3) ; Set when waiting for IRQ
40
41; IDE device only
42%ifdef MODULE_ADVANCED_ATA
43FLGH_DPT_IORDY EQU (1<<7) ; Controller and Drive supports IORDY
44%endif
45
46; Serial device only
47FLGH_DPT_SERIAL_FLOPPY EQU (1<<4)
48FLGH_DPT_SERIAL_FLOPPY_TYPE_MASK EQU 0e0h
49FLGH_DPT_SERIAL_FLOPPY_TYPE_FIELD_POSITION EQU 5
50
51; Addressing modes for DPT.wFlags
52ADDRESSING_MODE_FIELD_POSITION EQU 5
53ADDRESSING_MODE_LCHS EQU 0 ; L-CHS Addressing Mode (NORMAL in many other BIOSes)
54ADDRESSING_MODE_PCHS EQU 1 ; P-CHS Addressing Mode (LARGE in many other BIOSes)
55ADDRESSING_MODE_LBA28 EQU 2 ; 28-bit LBA Addressing Mode
56ADDRESSING_MODE_LBA48 EQU 3 ; 48-bit LBA Addressing Mode
57
58
59; DPT for ATA devices
60struc DPT_ATA ; 10 + 2 bytes = 12 bytes
61 .dpt resb DPT_size
62 .bBlockSize resb 1 ; Current block size in sectors (do not set to zero!)
63 .bInitError resb 1
64endstruc
65
66; Flags for BOOTMENUINFO.wInitErrorFlags
67FLG_INITERROR_FAILED_TO_SELECT_DRIVE EQU (1<<0)
68FLG_INITERROR_FAILED_TO_INITIALIZE_CHS_PARAMETERS EQU (1<<1)
69FLG_INITERROR_FAILED_TO_SET_WRITE_CACHE EQU (1<<2)
70FLG_INITERROR_FAILED_TO_RECALIBRATE_DRIVE EQU (1<<3)
71FLG_INITERROR_FAILED_TO_SET_BLOCK_MODE EQU (1<<4)
72FLG_INITERROR_FAILED_TO_SET_PIO_MODE EQU (1<<5)
73
74
75; Additional variables needed to initialize and reset Advanced IDE Controllers.
76; EBDA must be reserved for DPTs when using these!
77%ifdef MODULE_ADVANCED_ATA
78struc DPT_ADVANCED_ATA
79 .dpt_ata resb DPT_ATA_size
80 .wControllerID resb 2 ; Controller specific ID WORD (from Advanced Controller detection)
81 .wControllerBasePort resb 2 ; Advanced Controller port (not IDE port)
82 .wMinPioCycleTime resb 2 ; Minimum PIO Cycle Time in ns
83 .bPioMode resb 1 ; Best supported PIO mode
84 .bDevice resb 1 ; Device Type from IDEVARS (overrided when 32-bit controller detected)
85endstruc
86%endif
87
88
89; DPT for Serial devices
90%ifdef MODULE_SERIAL
91struc DPT_SERIAL
92 .dpt resb DPT_size
93 .wSerialPortAndBaud:
94 .bSerialPort resb 1 ; Serial connection I/O port address, divided by 4
95 .bSerialBaud resb 1 ; Serial connection baud rate divisor
96endstruc
97%endif
98
99
100; This is the common size for all DPTs. All DPTs must be equal size.
101%ifdef MODULE_ADVANCED_ATA
102LARGEST_DPT_SIZE EQU DPT_ADVANCED_ATA_size
103%else
104LARGEST_DPT_SIZE EQU DPT_ATA_size
105%endif
106
107
108; Number of Sectors per Track is fixed to 63 for LBA assist calculation.
109; 1024 cylinders, 256 heads, 63 sectors = 8.4 GB limit (but DOS does not support more than 255 heads)
110MAX_LCHS_CYLINDERS EQU 1024
111LBA_ASSIST_SPT EQU 63
112
113
114;--------------------------------------------------------------------
115; LIMIT_LBA_CYLINDERS_IN_DXAX_TO_LCHS_CYLINDERS
116; Parameters:
117; DX:AX: Number of LBA cylinders
118; Returns:
119; AX: Number of L-CHS cylinders
120; Corrupts registers:
121; Nothing
122;--------------------------------------------------------------------
123%macro LIMIT_LBA_CYLINDERS_IN_DXAX_TO_LCHS_CYLINDERS 0
124 test dx, dx
125 jnz SHORT %%LoadMaxValueToAX
126 cmp ax, MAX_LCHS_CYLINDERS
127 jb SHORT %%NoNeedToModify
128%%LoadMaxValueToAX:
129 mov ax, MAX_LCHS_CYLINDERS
130%%NoNeedToModify:
131%endmacro
132
133
134%endif ; CUSTOMDPT_INC
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