source: xtideuniversalbios/trunk/XTIDE_Universal_BIOS/Inc/Controllers/XTCF.inc@ 496

Last change on this file since 496 was 496, checked in by aitotat@…, 12 years ago

Changes to XTIDE Universal BIOS:

  • XT-CF related code in IdeIO_OutputALtoIdeControlBlockRegisterInDL is now properly included when MODULE_8BIT_IDE_ADVANCED is not available.
  • Added Control Block Registers offsets to RomVars.inc.
File size: 3.2 KB
Line 
1; Project name : XTIDE Universal BIOS
2; Description : Lo-tech XT-CFv2 board specifications.
3;
4; More information at http://www.lo-tech.co.uk/wiki/Lo-tech_XT-CFv2_Board
5
6;
7; XTIDE Universal BIOS and Associated Tools
8; Copyright (C) 2009-2010 by Tomi Tilli, 2011-2012 by XTIDE Universal BIOS Team.
9;
10; This program is free software; you can redistribute it and/or modify
11; it under the terms of the GNU General Public License as published by
12; the Free Software Foundation; either version 2 of the License, or
13; (at your option) any later version.
14;
15; This program is distributed in the hope that it will be useful,
16; but WITHOUT ANY WARRANTY; without even the implied warranty of
17; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18; GNU General Public License for more details.
19; Visit http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
20;
21
22%ifndef XTCF_INC
23%define XTCF_INC
24
25DEFAULT_XTCF_SECTOR_WINDOW_SEGMENT EQU 0D800h
26
27; XT-CF requires that block must be less than 128 sectors (64 kiB).
28; Instead of limiting block size to 64, we limit it to 32 (16 kiB).
29; Transferring more than 16 kiB with 8237 DMA controller block or demand
30; mode might interfere with DRAM refresh on XT systems.
31XTCF_DMA_MODE_MAX_BLOCK_SIZE EQU 32 ; Sectors
32
33; Possible base addresses. Note that all XT-CF IDE registers are SHL 1 compared
34; to standard IDE registers.
35XTCF_BASE_PORT_DETECTION_SEED EQU 140h ; Not a valid base address but needed for autodetection
36XTCF_BASE_PORT_1 EQU 200h
37XTCF_BASE_PORT_2 EQU 240h
38XTCF_BASE_PORT_3 EQU 300h ; Default setting
39XTCF_BASE_PORT_4 EQU 340h
40
41
42; XT-CF Control Register (do not SHL 1 these!)
43XTCF_CONTROL_REGISTER EQU 1Fh
44XTCF_CONTROL_REGISTER_INVERTED_in EQU 1Eh
45
46; Control Register contents:
47;
48; Control Register holds high byte from Sector Window segment if >= A0h
49; (First possible segment for Sector Window is A000h)
50;
51; 8-bit PIO transfers (port I/O) are used if Control Register is zero.
52; Any other value means DMA transfers (using DMA channel 3).
53XTCF_8BIT_PIO_MODE EQU 0
54XTCF_DMA_MODE EQU 10h
55XTCF_MEMORY_MAPPED_MODE EQU 0A0h
56RAISE_DRQ_AND_CLEAR_XTCF_XFER_COUNTER EQU 40h
57
58
59
60; Subcommands for AH=1Eh, Lo-tech XT-CF features.
61; Return values common for all subcommands:
62; AH: RET_HD_SUCCESS if drive is XT-CF
63; RET_HD_INVALID if drive is not XT-CF
64; CF: 0 if successful, 1 if error
65
66;--------------------------------------------------------------------
67; IS_THIS_DRIVE_XTCF
68; Parameters:
69; DL: Drive Number
70;--------------------------------------------------------------------
71IS_THIS_DRIVE_XTCF EQU 0
72
73;--------------------------------------------------------------------
74; READ_XTCF_CONTROL_REGISTER_TO_DH
75; Parameters:
76; DL: Drive Number
77; Returns:
78; DH: XT-CF Control Register contents
79;--------------------------------------------------------------------
80READ_XTCF_CONTROL_REGISTER_TO_DH EQU 1
81
82;--------------------------------------------------------------------
83; WRITE_DH_TO_XTCF_CONTROL_REGISTER
84; Parameters:
85; DH: Byte to write to XT-CF Control Register
86; DL: Drive Number
87;--------------------------------------------------------------------
88WRITE_DH_TO_XTCF_CONTROL_REGISTER EQU 2
89
90
91%endif ; XTCF_INC
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