| 1 | ; Project name : XTIDE Universal BIOS
|
|---|
| 2 | ; Description : Lo-tech XT-CFv2 board specifications.
|
|---|
| 3 | ;
|
|---|
| 4 | ; More information at http://www.lo-tech.co.uk/wiki/Lo-tech_XT-CFv2_Board
|
|---|
| 5 |
|
|---|
| 6 | ;
|
|---|
| 7 | ; XTIDE Universal BIOS and Associated Tools
|
|---|
| 8 | ; Copyright (C) 2009-2010 by Tomi Tilli, 2011-2012 by XTIDE Universal BIOS Team.
|
|---|
| 9 | ;
|
|---|
| 10 | ; This program is free software; you can redistribute it and/or modify
|
|---|
| 11 | ; it under the terms of the GNU General Public License as published by
|
|---|
| 12 | ; the Free Software Foundation; either version 2 of the License, or
|
|---|
| 13 | ; (at your option) any later version.
|
|---|
| 14 | ;
|
|---|
| 15 | ; This program is distributed in the hope that it will be useful,
|
|---|
| 16 | ; but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|---|
| 17 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|---|
| 18 | ; GNU General Public License for more details.
|
|---|
| 19 | ; Visit http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
|
|---|
| 20 | ;
|
|---|
| 21 |
|
|---|
| 22 | %ifndef XTCF_INC
|
|---|
| 23 | %define XTCF_INC
|
|---|
| 24 |
|
|---|
| 25 | ; Possible base addresses. Note that all XT-CF IDE registers are SHL 1 compared
|
|---|
| 26 | ; to standard IDE registers.
|
|---|
| 27 | XTCF_BASE_PORT_1 EQU 200h
|
|---|
| 28 | XTCF_BASE_PORT_2 EQU 240h
|
|---|
| 29 | XTCF_BASE_PORT_3 EQU 300h ; Default setting
|
|---|
| 30 | XTCF_BASE_PORT_4 EQU 320h
|
|---|
| 31 |
|
|---|
| 32 |
|
|---|
| 33 | ; XT-CF Control Register (do not SHL 1 these!)
|
|---|
| 34 | XTCF_CONTROL_REGISTER EQU 1Fh
|
|---|
| 35 | XTCT_CONTROL_REGISTER_INVERTED_in EQU 1Eh
|
|---|
| 36 |
|
|---|
| 37 |
|
|---|
| 38 | ; Bit Definitions for XT-CF Control Register
|
|---|
| 39 | MASK_XTCF_BASE_PORT_in EQU (3<<0) ; Bits 0...1
|
|---|
| 40 | XTCF_PORT_200h EQU 0
|
|---|
| 41 | XTCF_PORT_240h EQU 1
|
|---|
| 42 | XTCF_PORT_300h EQU 2 ; Default
|
|---|
| 43 | XTCF_PORT_320h EQU 3
|
|---|
| 44 | FLG_PIO8_INSTEAD_OF_DMA EQU (1<<2) ; Set to enable PIO8, clear to enable DMA (Channel 3)
|
|---|
| 45 | FLG_AT_ZERO_WAIT_STATE_in EQU (1<<3)
|
|---|
| 46 | MASK_SECTOR_WINDOW_SEGMENT_in EQU (7<<4) ; Bits 4...6
|
|---|
| 47 | XTCF_SECTOR_WINDOW_AT_C000h EQU 0
|
|---|
| 48 | XTCF_SECTOR_WINDOW_AT_C800h EQU 1
|
|---|
| 49 | XTCF_SECTOR_WINDOW_AT_D000h EQU 2 ; Default
|
|---|
| 50 | XTCF_SECTOR_WINDOW_AT_D800h EQU 3
|
|---|
| 51 | XTCF_SECTOR_WINDOW_AT_E000h EQU 4
|
|---|
| 52 | XTCF_SECTOR_WINDOW_AT_E800h EQU 5
|
|---|
| 53 | FLG_XTCF_ROM_ENABLE_in EQU (1<<7)
|
|---|
| 54 |
|
|---|
| 55 |
|
|---|
| 56 | %endif ; XTCF_INC
|
|---|
