source: xtideuniversalbios/trunk/XTIDE_Universal_BIOS/Inc/Controllers/Vision.inc@ 420

Last change on this file since 420 was 376, checked in by gregli@…, 13 years ago

WIDE checkin... Added copyright and license information to sorce files, as per the GPL instructions for usage.

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1; Project name : XTIDE Universal BIOS
2; Description : QDI Vision QD6500 and QD6580 VLB IDE controller
3; specifications.
4;
5; Specifications can be found at http://www.ryston.cz/petr/vlb/vlbidechips.html
6; QD6580 DOS Driver Analysis: http://www.ryston.cz/petr/qd/dos37.html
7
8;
9; XTIDE Universal BIOS and Associated Tools
10; Copyright (C) 2009-2010 by Tomi Tilli, 2011-2012 by XTIDE Universal BIOS Team.
11;
12; This program is free software; you can redistribute it and/or modify
13; it under the terms of the GNU General Public License as published by
14; the Free Software Foundation; either version 2 of the License, or
15; (at your option) any later version.
16;
17; This program is distributed in the hope that it will be useful,
18; but WITHOUT ANY WARRANTY; without even the implied warranty of
19; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20; GNU General Public License for more details.
21; Visit http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
22;
23
24%ifndef VISION_INC
25%define VISION_INC
26
27; Possible base addresses for QD6500 and QD6580
28QD65XX_BASE_PORT EQU 30h
29QD65XX_ALTERNATIVE_BASE_PORT EQU 0B0h
30
31
32; Vision Register offsets from QD chip base port
33QD6500_IDE_TIMING_REGISTER EQU 0
34QD6580_PRIMARY_IDE_TIMING_REGISTER EQU 0 ; QD6500 has only one channel
35QD65XX_CONFIG_REGISTER_in EQU 1
36QD6580_SECONDARY_IDE_TIMING_REGISTER EQU 2 ; Same definitions as Primary IDE Timing Register
37QD6580_CONTROL_REGISTER EQU 3
38
39
40; Bit definitions for QD65xx IDE Timing Register(s)
41MASK_QD6500IDE_ACTIVE_TIME EQU 7h ; Active time in VLB clocks (bits 0...2)
42 ; 000b = 8 clocks (<= 33 MHz), 9 clocks (>33 MHz)
43 ; 111b = 1 clock (<= 33 MHz), 2 clocks (>33 MHz)
44MASK_QD6580IDE_ACTIVE_TIME EQU 0Fh ; Active time in VLB clocks (bits 0...3)
45 ; 0000b = 17 clocks, 1111b = 2 clocks
46
47MASK_QD6500IDE_RECOVERY_TIME EQU 0F0h ; Recovery time in VLB clocks (bits 4...7)
48 ; 0000b = 18 clocks (<= 33 MHz), 15 clocks (>33 MHz)
49 ; 1111b = 3 clocks (<= 33 MHz), 0 clocks (>33 MHz)
50MASK_QD6580IDE_RECOVERY_TIME EQU MASK_QD6500IDE_RECOVERY_TIME
51 ; 0000b = 15 clocks, 1101b = 2 clocks
52POSITON_QD65XXIDE_RECOVERY_TIME EQU 4
53
54
55; Bit definitions for QD65xx Config Register (read only)
56FLG_QDCONFIG_PRIMARY_IDE EQU (1<<0) ; IDE Controller Base Address
57 ; 0 = 170h, 1 = 1F0h
58FLG_QDCONFIG_ALTERNATIVE_BASE EQU (1<<1) ; QD Vision Controller Base Address
59 ; 0 = 30h, 1 = B0h
60FLG_QDCONFIG_ID3 EQU (1<<2) ; VLB bus speed
61 ; 0 = > 33 MHz, 1 = <= 33 MHz
62FLG_QDCONFIG_QD6500STATUS EQU (1<<3) ; QD6500 Enabled/Disabled status
63 ; 0 = Enabled, 1 = Disabled
64MASK_QDCONFIG_CONTROLLER_ID EQU 0F0h ; QDI Vision Controller Identification nibble
65
66; QDI Vision Controller Identification nibbles
67ID_QD6500 EQU 1100b
68ID_QD6580 EQU 1010b
69ID_QD6580_ALTERNATE EQU 0101b
70
71
72; Bit definitions for QD6580 Control Register
73FLG_QDCONTROL_SECONDARY_DISABLED_in EQU (1<<0) ; 0 = Primary and Secondary IDE enabled (Primary at 1F0h and Secondary at 170h)
74 ; 1 = Only Primary IDE enabled (always at 1F0h)
75FLG_QDCONTROL_HDONLY_in EQU (1<<1) ; 0 = Hard drive or ATAPI device
76 ; 1 = Hard drives only
77FLG_QDCONTROL_NONATAPI EQU (1<<7) ; Set to 1 for non-ATAPI devices (hard drives,
78 ; probably Read ahead and/or post-write control?)
79MASK_QDCONTROL_FLAGS_TO_SET EQU 01011111b ; Bits that must be set when writing the Control Register
80
81
82
83; Minimum and Maximum Active and Recovery Time Values
84QD6500_MAX_ACTIVE_TIME_CLOCKS EQU 8 ; VLB clocks
85QD6500_MIN_ACTIVE_TIME_CLOCKS EQU 1 ; VLB clocks
86QD6580_MAX_ACTIVE_TIME_CLOCKS EQU 17 ; VLB clocks
87QD6580_MIN_ACTIVE_TIME_CLOCKS EQU 2 ; VLB clocks
88QD65xx_MAX_RECOVERY_TIME_CLOCKS EQU 15 ; VLB clocks
89QD65xx_MIN_RECOVERY_TIME_CLOCKS EQU 2 ; VLB clocks
90
91
92; Cycle times for different VLB bus clocks
93VLB_33MHZ_CYCLE_TIME EQU 30 ; ns
94VLB_40MHZ_CYCLE_TIME EQU 25 ; ns
95
96
97%endif ; VISION_INC
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