source: xtideuniversalbios/trunk/XTIDE_Universal_BIOS/Inc/Controllers/Vision.inc@ 363

Last change on this file since 363 was 363, checked in by aitotat@…, 13 years ago

Changes to XTIDE Universal BIOS:

  • Added Advanced ATA Module (MODULE_ADVANCED_ATA) with native support for QDI Vision QD6500 and QD6580 VLB IDE Controllers.
  • Hopefully optimized IDE transfer functions for 8088 (replaced some memory accesses from WORD to BYTE).
  • XT build does not fit in 8k at the moment!!!
File size: 3.3 KB
Line 
1; Project name : XTIDE Universal BIOS
2; Description : QDI Vision QD6500 and QD6580 VLB IDE controller
3; specifications.
4;
5; Specifications can be found at http://www.ryston.cz/petr/vlb/vlbidechips.html
6; QD6580 DOS Driver Analysis: http://www.ryston.cz/petr/qd/dos37.html
7%ifndef VISION_INC
8%define VISION_INC
9
10; Possible base addresses for QD6500 and QD6580
11QD65XX_BASE_PORT EQU 30h
12QD65XX_ALTERNATIVE_BASE_PORT EQU 0B0h
13
14
15; Vision Register offsets from QD chip base port
16QD6500_IDE_TIMING_REGISTER EQU 0
17QD6580_PRIMARY_IDE_TIMING_REGISTER EQU 0 ; QD6500 has only one channel
18QD65XX_CONFIG_REGISTER_in EQU 1
19QD6580_SECONDARY_IDE_TIMING_REGISTER EQU 2 ; Same definitions as Primary IDE Timing Register
20QD6580_CONTROL_REGISTER EQU 3
21
22
23; Bit definitions for QD65xx IDE Timing Register(s)
24MASK_QD6500IDE_ACTIVE_TIME EQU 7h ; Active time in VLB clocks (bits 0...2)
25 ; 000b = 8 clocks (<= 33 MHz), 9 clocks (>33 MHz)
26 ; 111b = 1 clock (<= 33 MHz), 2 clocks (>33 MHz)
27MASK_QD6580IDE_ACTIVE_TIME EQU 0Fh ; Active time in VLB clocks (bits 0...3)
28 ; 0000b = 17 clocks, 1111b = 2 clocks
29
30MASK_QD6500IDE_RECOVERY_TIME EQU 0F0h ; Recovery time in VLB clocks (bits 4...7)
31 ; 0000b = 18 clocks (<= 33 MHz), 15 clocks (>33 MHz)
32 ; 1111b = 3 clocks (<= 33 MHz), 0 clocks (>33 MHz)
33MASK_QD6580IDE_RECOVERY_TIME EQU MASK_QD6500IDE_RECOVERY_TIME
34 ; 0000b = 15 clocks, 1101b = 2 clocks
35POSITON_QD65XXIDE_RECOVERY_TIME EQU 4
36
37
38; Bit definitions for QD65xx Config Register (read only)
39FLG_QDCONFIG_PRIMARY_IDE EQU (1<<0) ; IDE Controller Base Address
40 ; 0 = 170h, 1 = 1F0h
41FLG_QDCONFIG_ALTERNATIVE_BASE EQU (1<<1) ; QD Vision Controller Base Address
42 ; 0 = 30h, 1 = B0h
43FLG_QDCONFIG_ID3 EQU (1<<2) ; VLB bus speed
44 ; 0 = > 33 MHz, 1 = <= 33 MHz
45FLG_QDCONFIG_QD6500STATUS EQU (1<<3) ; QD6500 Enabled/Disabled status
46 ; 0 = Enabled, 1 = Disabled
47MASK_QDCONFIG_CONTROLLER_ID EQU 0F0h ; QDI Vision Controller Identification nibble
48
49; QDI Vision Controller Identification nibbles
50ID_QD6500 EQU 1100b
51ID_QD6580 EQU 1010b
52ID_QD6580_ALTERNATE EQU 0101b
53
54
55; Bit definitions for QD6580 Control Register
56FLG_QDCONTROL_SECONDARY_DISABLED_in EQU (1<<0) ; 0 = Primary and Secondary IDE enabled (Primary at 1F0h and Secondary at 170h)
57 ; 1 = Only Primary IDE enabled (always at 1F0h)
58FLG_QDCONTROL_HDONLY_in EQU (1<<1) ; 0 = Hard drive or ATAPI device
59 ; 1 = Hard drives only
60FLG_QDCONTROL_NONATAPI EQU (1<<7) ; Set to 1 for non-ATAPI devices (hard drives,
61 ; probably Read ahead and/or post-write control?)
62MASK_QDCONTROL_FLAGS_TO_SET EQU 01011111b ; Bits that must be set when writing the Control Register
63
64
65
66; Minimum and Maximum Active and Recovery Time Values
67QD6500_MAX_ACTIVE_TIME_CLOCKS EQU 8 ; VLB clocks
68QD6500_MIN_ACTIVE_TIME_CLOCKS EQU 1 ; VLB clocks
69QD6580_MAX_ACTIVE_TIME_CLOCKS EQU 17 ; VLB clocks
70QD6580_MIN_ACTIVE_TIME_CLOCKS EQU 2 ; VLB clocks
71QD65xx_MAX_RECOVERY_TIME_CLOCKS EQU 15 ; VLB clocks
72QD65xx_MIN_RECOVERY_TIME_CLOCKS EQU 2 ; VLB clocks
73
74
75; Cycle times for different VLB bus clocks
76VLB_33MHZ_CYCLE_TIME EQU 30 ; ns
77VLB_40MHZ_CYCLE_TIME EQU 25 ; ns
78
79
80%endif ; VISION_INC
Note: See TracBrowser for help on using the repository browser.