source: xtideuniversalbios/trunk/XTIDE_Universal_BIOS/Inc/Controllers/ADP50L.inc@ 612

Last change on this file since 612 was 536, checked in by krille_n_@…, 12 years ago

Changes:

  • Added support for the Silicon Valley Computer ADP50L controller (and possibly other IDE controllers from SVC using memory mapped I/O). Please note that this has not been tested in any way since I don't have any of these cards myself (make backups before trying this on drives with important data). Also, *if* it works, make sure it works reliably (stress test the disk system). Some things you should know: 1) Autodetection for this controller has not been added to XTIDECFG, you need to manually select the "SVC ADP50L" controller (and possibly change the BIOS segment address if not using the default of C800h). 2) The memory mapped I/O window is inside the ROM address space of the controller. The XTIDE Universal BIOS currently do not support this so that means you need to use another ROM (for example, an XTIDE or XTCF card or the BOOT ROM of a NIC). This presents another problem, the original ADP50L BIOS needs to be disabled somehow to avoid conflicts. Either pull the ROM chip or disable the BIOS by removing jumper J3. Note, I have no idea if any of this will actually work. It's basically a shot in the dark.
File size: 2.0 KB
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1; Project name : XTIDE Universal BIOS
2; Description : Silicon Valley Computer ADP50L specifications.
3
4;
5; XTIDE Universal BIOS and Associated Tools
6; Copyright (C) 2009-2010 by Tomi Tilli, 2011-2013 by XTIDE Universal BIOS Team.
7;
8; This program is free software; you can redistribute it and/or modify
9; it under the terms of the GNU General Public License as published by
10; the Free Software Foundation; either version 2 of the License, or
11; (at your option) any later version.
12;
13; This program is distributed in the hope that it will be useful,
14; but WITHOUT ANY WARRANTY; without even the implied warranty of
15; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16; GNU General Public License for more details.
17; Visit http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
18;
19
20%ifndef ADP50L_INC
21%define ADP50L_INC
22
23; | BIOS Segment --------- | Unknown - | ROM Chip ---------- |
24; Jumper: J1 J2 J3 J4 J5 J6 J7
25; Disabled N/A N/A OFF OFF OFF OFF OFF = 2764 / 27C64 *
26; C800h * OFF OFF ON ON = 27256 / 27C256
27; CA00h ON OFF ON
28; CC00h OFF ON ON
29; CE00h ON ON ON
30;
31; * Defaults
32; Unknown = "Factory configured - do not alter"
33; Bits 11...9 of the segment address corresponds to jumpers J3...J1.
34
35ADP50L_BIOS_SEGMENT_ADDRESS_1 EQU 0C800h ; Default
36ADP50L_BIOS_SEGMENT_ADDRESS_2 EQU 0CA00h
37ADP50L_BIOS_SEGMENT_ADDRESS_3 EQU 0CC00h
38ADP50L_BIOS_SEGMENT_ADDRESS_4 EQU 0CE00h
39ADP50L_DEFAULT_BIOS_SEGMENT_ADDRESS EQU ADP50L_BIOS_SEGMENT_ADDRESS_1
40
41; Offsets from BIOS segment address
42ADP50L_COMMAND_BLOCK_REGISTER_WINDOW_OFFSET EQU 1D00h
43ADP50L_CONTROL_BLOCK_REGISTER_WINDOW_OFFSET EQU 1D10h ; The low byte is (8 SHL 1)
44ADP50L_SECTOR_ACCESS_WINDOW_OFFSET EQU 1E00h ; 512 byte IDE Sector Access Window
45
46; All IDE register offsets are SHL 1 compared to the standard offsets.
47; Example 1: STATUS_REGISTER_in = ADP50L_COMMAND_BLOCK_REGISTER_WINDOW_OFFSET + (STATUS_REGISTER_in << 1)
48; Example 2: DEVICE_CONTROL_REGISTER_out = ADP50L_CONTROL_BLOCK_REGISTER_WINDOW_OFFSET + (DEVICE_CONTROL_REGISTER_out << 1)
49
50%endif ; ADP50L_INC
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